ARM: perf: allow armpmu to implement mode exclusion
Modern PMUs allow for mode exclusion, so we no longer wish to return -EPERM if it is requested. This patch provides a hook in the armpmu structure for implementing mode exclusion. The hw_perf_event initialisation is slightly delayed so that the backend code can update the structure if required. Acked-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -75,6 +75,8 @@ struct arm_pmu {
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void (*disable)(struct hw_perf_event *evt, int idx);
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int (*get_event_idx)(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc);
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int (*set_event_filter)(struct hw_perf_event *evt,
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struct perf_event_attr *attr);
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u32 (*read_counter)(int idx);
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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@ -477,6 +479,13 @@ hw_perf_event_destroy(struct perf_event *event)
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}
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}
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static int
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event_requires_mode_exclusion(struct perf_event_attr *attr)
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{
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return attr->exclude_idle || attr->exclude_user ||
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attr->exclude_kernel || attr->exclude_hv;
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}
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static int
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__hw_perf_event_init(struct perf_event *event)
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{
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@ -502,34 +511,31 @@ __hw_perf_event_init(struct perf_event *event)
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}
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/*
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* Check whether we need to exclude the counter from certain modes.
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* The ARM performance counters are on all of the time so if someone
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* has asked us for some excludes then we have to fail.
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet. For SMP systems, each core has it's own PMU so we can't do any
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* clever allocation or constraints checking at this point.
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*/
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if (event->attr.exclude_kernel || event->attr.exclude_user ||
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event->attr.exclude_hv || event->attr.exclude_idle) {
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hwc->idx = -1;
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hwc->config_base = 0;
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hwc->config = 0;
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hwc->event_base = 0;
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/*
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* Check whether we need to exclude the counter from certain modes.
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*/
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if ((!armpmu->set_event_filter ||
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armpmu->set_event_filter(hwc, &event->attr)) &&
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event_requires_mode_exclusion(&event->attr)) {
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pr_debug("ARM performance counters do not support "
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"mode exclusion\n");
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return -EPERM;
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}
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/*
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet. For SMP systems, each core has it's own PMU so we can't do any
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* clever allocation or constraints checking at this point.
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* Store the event encoding into the config_base field.
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*/
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hwc->idx = -1;
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/*
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* Store the event encoding into the config_base field. config and
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* event_base are unused as the only 2 things we need to know are
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* the event mapping and the counter to use. The counter to use is
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* also the indx and the config_base is the event type.
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*/
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hwc->config_base = (unsigned long)mapping;
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hwc->config = 0;
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hwc->event_base = 0;
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hwc->config_base |= (unsigned long)mapping;
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if (!hwc->sample_period) {
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hwc->sample_period = armpmu->max_period;
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