amd64_edac: check NB MCE bank enable on the current node properly
The old code was using smp_call_function_many which skips the current cpu if it is in the supplied cpumask. Switch to the rdmsr_on_cpus() interface which takes care of that. In addition, add get_cpus_on_this_dct_cpumask helper which computes a cpumask of all the cores on a node and thus on a DCT. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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57a30854c8
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06724535f8
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@ -2741,30 +2741,53 @@ static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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}
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static void check_mcg_ctl(void *ret)
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/* get all cores on this DCT */
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static void get_cpus_on_this_dct_cpumask(cpumask_t *mask, int nid)
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{
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u64 msr_val = 0;
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u8 nbe;
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int cpu;
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rdmsrl(MSR_IA32_MCG_CTL, msr_val);
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nbe = msr_val & K8_MSR_MCGCTL_NBE;
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debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
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raw_smp_processor_id(), msr_val,
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(nbe ? "enabled" : "disabled"));
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if (!nbe)
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*(int *)ret = 0;
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for_each_online_cpu(cpu)
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if (amd_get_nb_id(cpu) == nid)
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cpumask_set_cpu(cpu, mask);
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}
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/* check MCG_CTL on all the cpus on this node */
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static int mcg_ctl_enabled_on_node(const struct cpumask *mask)
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static bool amd64_nb_mce_bank_enabled_on_node(int nid)
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{
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int ret = 1;
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preempt_disable();
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smp_call_function_many(mask, check_mcg_ctl, &ret, 1);
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preempt_enable();
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cpumask_t mask;
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struct msr *msrs;
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int cpu, nbe, idx = 0;
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bool ret = false;
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cpumask_clear(&mask);
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get_cpus_on_this_dct_cpumask(&mask, nid);
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msrs = kzalloc(sizeof(struct msr) * cpumask_weight(&mask), GFP_KERNEL);
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if (!msrs) {
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amd64_printk(KERN_WARNING, "%s: error allocating msrs\n",
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__func__);
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return false;
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}
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rdmsr_on_cpus(&mask, MSR_IA32_MCG_CTL, msrs);
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for_each_cpu(cpu, &mask) {
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nbe = msrs[idx].l & K8_MSR_MCGCTL_NBE;
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debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
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cpu, msrs[idx].q,
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(nbe ? "enabled" : "disabled"));
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if (!nbe)
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goto out;
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idx++;
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}
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ret = true;
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out:
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kfree(msrs);
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return ret;
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}
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@ -2783,7 +2806,8 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
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{
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u32 value;
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int err = 0;
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u8 ecc_enabled = 0, mcg_ctl_en = 0;
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u8 ecc_enabled = 0;
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bool nb_mce_en = false;
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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@ -2797,13 +2821,13 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
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else
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amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n");
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mcg_ctl_en = mcg_ctl_enabled_on_node(cpumask_of_node(pvt->mc_node_id));
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if (!mcg_ctl_en)
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nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id);
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if (!nb_mce_en)
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amd64_printk(KERN_WARNING, "NB MCE bank disabled, set MSR "
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"0x%08x[4] on node %d to enable.\n",
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MSR_IA32_MCG_CTL, pvt->mc_node_id);
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if (!ecc_enabled || !mcg_ctl_en) {
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if (!ecc_enabled || !nb_mce_en) {
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if (!ecc_enable_override) {
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amd64_printk(KERN_WARNING, "%s", ecc_warning);
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return -ENODEV;
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