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MLK-18997: mtd: fsl-quadspi: disable the TDH DDR enable bit if it's been set 

for 6UL/7D, the TDH bit should only be set when DDR mode enabled. This
bit cannot be cleared during module reset, so check this bit in
nor_setup to make sure it cleard and won't affect the following
operations.

Signed-off-by: Han Xu <han.xu@nxp.com>
pull/10/head
Han Xu 2018-09-28 10:40:09 -05:00 committed by Jason Liu
parent c72818eb0e
commit 06b8684638
1 changed files with 4 additions and 0 deletions
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4
drivers/mtd/spi-nor/fsl-quadspi.c
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@ -821,6 +821,10 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
| QUADSPI_SMPR_HSENA_MASK
| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
/* disable the TDH bit of FLSHCR if it's been set*/
reg = qspi_readl(q, base + QUADSPI_FLSHCR);
qspi_writel(q, reg & ~QUADSPI_FLSHCR_TDH_MASK, base + QUADSPI_FLSHCR);
/* Enable the module */
qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
base + QUADSPI_MCR);