NFC: pn544: i2c: Add firmware download implementation for pn544
The pn544 can enter a firmware update mode where firmware blobs can be pushed through the i2c line and flashed on the target. A special command allows to verify that blobs are correctly flashed and this is what we do for every downloaded firmware blob. Signed-off-by: Eric Lapuyade <eric.lapuyade@intel.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Eric Lapuyade
Samuel Ortiz
parent
8bd7fc8995
commit
06c660340f
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@ -25,11 +25,14 @@
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#include <linux/miscdevice.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/nfc.h>
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#include <linux/firmware.h>
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#include <linux/unaligned/access_ok.h>
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#include <linux/platform_data/pn544.h>
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#include <net/nfc/hci.h>
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#include <net/nfc/llc.h>
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#include <net/nfc/nfc.h>
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#include "pn544.h"
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@ -55,6 +58,58 @@ MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table);
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#define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
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#define PN544_FW_CMD_WRITE 0x08
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#define PN544_FW_CMD_CHECK 0x06
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struct pn544_i2c_fw_frame_write {
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u8 cmd;
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u16 be_length;
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u8 be_dest_addr[3];
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u16 be_datalen;
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u8 data[];
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} __packed;
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struct pn544_i2c_fw_frame_check {
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u8 cmd;
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u16 be_length;
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u8 be_start_addr[3];
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u16 be_datalen;
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u16 be_crc;
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} __packed;
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struct pn544_i2c_fw_frame_response {
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u8 status;
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u16 be_length;
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} __packed;
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struct pn544_i2c_fw_blob {
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u32 be_size;
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u32 be_destaddr;
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u8 data[];
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};
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#define PN544_FW_CMD_RESULT_TIMEOUT 0x01
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#define PN544_FW_CMD_RESULT_BAD_CRC 0x02
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#define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
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#define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
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#define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
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#define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
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#define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
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#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
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#define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
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#define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
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#define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
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#define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
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PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
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PN544_FW_WRITE_BUFFER_MAX_LEN)
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#define FW_WORK_STATE_IDLE 1
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#define FW_WORK_STATE_START 2
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#define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
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#define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
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struct pn544_i2c_phy {
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struct i2c_client *i2c_dev;
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struct nfc_hci_dev *hdev;
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@ -64,6 +119,16 @@ struct pn544_i2c_phy {
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unsigned int gpio_fw;
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unsigned int en_polarity;
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struct work_struct fw_work;
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int fw_work_state;
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char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1];
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const struct firmware *fw;
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u32 fw_blob_dest_addr;
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size_t fw_blob_size;
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const u8 *fw_blob_data;
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size_t fw_written;
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int fw_cmd_result;
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int powered;
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int run_mode;
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@ -313,6 +378,42 @@ flush:
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return r;
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}
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static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy)
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{
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int r;
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struct pn544_i2c_fw_frame_response response;
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struct i2c_client *client = phy->i2c_dev;
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r = i2c_master_recv(client, (char *) &response, sizeof(response));
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if (r != sizeof(response)) {
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dev_err(&client->dev, "cannot read fw status\n");
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return -EIO;
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}
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usleep_range(3000, 6000);
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switch (response.status) {
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case 0:
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return 0;
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case PN544_FW_CMD_RESULT_TIMEOUT:
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return -ETIMEDOUT;
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case PN544_FW_CMD_RESULT_BAD_CRC:
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return -ENODATA;
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case PN544_FW_CMD_RESULT_ACCESS_DENIED:
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return -EACCES;
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case PN544_FW_CMD_RESULT_PROTOCOL_ERROR:
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return -EPROTO;
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case PN544_FW_CMD_RESULT_INVALID_PARAMETER:
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return -EINVAL;
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case PN544_FW_CMD_RESULT_INVALID_LENGTH:
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return -EBADMSG;
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case PN544_FW_CMD_RESULT_WRITE_FAILED:
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return -EIO;
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default:
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return -EIO;
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}
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}
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/*
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* Reads an shdlc frame from the chip. This is not as straightforward as it
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* seems. There are cases where we could loose the frame start synchronization.
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@ -347,19 +448,23 @@ static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id)
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if (phy->hard_fault != 0)
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return IRQ_HANDLED;
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r = pn544_hci_i2c_read(phy, &skb);
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if (r == -EREMOTEIO) {
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phy->hard_fault = r;
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if (phy->run_mode == PN544_FW_MODE) {
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phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy);
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schedule_work(&phy->fw_work);
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} else {
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r = pn544_hci_i2c_read(phy, &skb);
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if (r == -EREMOTEIO) {
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phy->hard_fault = r;
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nfc_hci_recv_frame(phy->hdev, NULL);
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nfc_hci_recv_frame(phy->hdev, NULL);
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return IRQ_HANDLED;
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} else if ((r == -ENOMEM) || (r == -EBADMSG)) {
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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} else if ((r == -ENOMEM) || (r == -EBADMSG)) {
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return IRQ_HANDLED;
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}
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nfc_hci_recv_frame(phy->hdev, skb);
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}
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nfc_hci_recv_frame(phy->hdev, skb);
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return IRQ_HANDLED;
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}
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@ -369,6 +474,215 @@ static struct nfc_phy_ops i2c_phy_ops = {
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.disable = pn544_hci_i2c_disable,
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};
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static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name)
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{
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struct pn544_i2c_phy *phy = phy_id;
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pr_info(DRIVER_DESC ": Starting Firmware Download (%s)\n",
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firmware_name);
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strcpy(phy->firmware_name, firmware_name);
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phy->fw_work_state = FW_WORK_STATE_START;
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schedule_work(&phy->fw_work);
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return 0;
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}
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static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy,
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int result)
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{
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pr_info(DRIVER_DESC ": Firmware Download Complete, result=%d\n", result);
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pn544_hci_i2c_disable(phy);
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phy->fw_work_state = FW_WORK_STATE_IDLE;
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if (phy->fw) {
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release_firmware(phy->fw);
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phy->fw = NULL;
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}
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nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result);
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}
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static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr,
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const u8 *data, u16 datalen)
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{
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u8 frame[PN544_FW_I2C_MAX_PAYLOAD];
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struct pn544_i2c_fw_frame_write *framep;
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u16 params_len;
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int framelen;
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int r;
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if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN)
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datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN;
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framep = (struct pn544_i2c_fw_frame_write *) frame;
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params_len = sizeof(framep->be_dest_addr) +
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sizeof(framep->be_datalen) + datalen;
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framelen = params_len + sizeof(framep->cmd) +
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sizeof(framep->be_length);
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framep->cmd = PN544_FW_CMD_WRITE;
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put_unaligned_be16(params_len, &framep->be_length);
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framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16;
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framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8;
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framep->be_dest_addr[2] = dest_addr & 0xff;
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put_unaligned_be16(datalen, &framep->be_datalen);
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memcpy(framep->data, data, datalen);
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r = i2c_master_send(client, frame, framelen);
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if (r == framelen)
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return datalen;
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else if (r < 0)
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return r;
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else
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return -EIO;
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}
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static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr,
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const u8 *data, u16 datalen)
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{
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struct pn544_i2c_fw_frame_check frame;
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int r;
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u16 crc;
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/* calculate local crc for the data we want to check */
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crc = crc_ccitt(0xffff, data, datalen);
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frame.cmd = PN544_FW_CMD_CHECK;
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put_unaligned_be16(sizeof(frame.be_start_addr) +
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sizeof(frame.be_datalen) + sizeof(frame.be_crc),
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&frame.be_length);
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/* tell the chip the memory region to which our crc applies */
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frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16;
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frame.be_start_addr[1] = (start_addr & 0xff00) >> 8;
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frame.be_start_addr[2] = start_addr & 0xff;
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put_unaligned_be16(datalen, &frame.be_datalen);
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/*
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* and give our local crc. Chip will calculate its own crc for the
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* region and compare with ours.
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*/
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put_unaligned_be16(crc, &frame.be_crc);
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r = i2c_master_send(client, (const char *) &frame, sizeof(frame));
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if (r == sizeof(frame))
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return 0;
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else if (r < 0)
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return r;
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else
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return -EIO;
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}
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static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy)
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{
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int r;
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r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev,
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phy->fw_blob_dest_addr + phy->fw_written,
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phy->fw_blob_data + phy->fw_written,
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phy->fw_blob_size - phy->fw_written);
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if (r < 0)
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return r;
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phy->fw_written += r;
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phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER;
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return 0;
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}
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static void pn544_hci_i2c_fw_work(struct work_struct *work)
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{
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struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy,
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fw_work);
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int r;
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struct pn544_i2c_fw_blob *blob;
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switch (phy->fw_work_state) {
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case FW_WORK_STATE_START:
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pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
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r = request_firmware(&phy->fw, phy->firmware_name,
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&phy->i2c_dev->dev);
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if (r < 0)
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goto exit_state_start;
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blob = (struct pn544_i2c_fw_blob *) phy->fw->data;
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phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
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phy->fw_blob_dest_addr = get_unaligned_be32(&blob->be_destaddr);
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phy->fw_blob_data = blob->data;
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phy->fw_written = 0;
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r = pn544_hci_i2c_fw_write_chunk(phy);
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exit_state_start:
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if (r < 0)
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pn544_hci_i2c_fw_work_complete(phy, r);
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break;
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case FW_WORK_STATE_WAIT_WRITE_ANSWER:
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r = phy->fw_cmd_result;
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if (r < 0)
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goto exit_state_wait_write_answer;
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if (phy->fw_written == phy->fw_blob_size) {
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r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev,
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phy->fw_blob_dest_addr,
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phy->fw_blob_data,
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phy->fw_blob_size);
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if (r < 0)
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goto exit_state_wait_write_answer;
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phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER;
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break;
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}
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r = pn544_hci_i2c_fw_write_chunk(phy);
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exit_state_wait_write_answer:
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if (r < 0)
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pn544_hci_i2c_fw_work_complete(phy, r);
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break;
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case FW_WORK_STATE_WAIT_CHECK_ANSWER:
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r = phy->fw_cmd_result;
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if (r < 0)
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goto exit_state_wait_check_answer;
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blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data +
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phy->fw_blob_size);
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phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
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if (phy->fw_blob_size != 0) {
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phy->fw_blob_dest_addr =
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get_unaligned_be32(&blob->be_destaddr);
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phy->fw_blob_data = blob->data;
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phy->fw_written = 0;
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r = pn544_hci_i2c_fw_write_chunk(phy);
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}
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exit_state_wait_check_answer:
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if (r < 0 || phy->fw_blob_size == 0)
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pn544_hci_i2c_fw_work_complete(phy, r);
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break;
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default:
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break;
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}
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}
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static int pn544_hci_i2c_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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@ -392,6 +706,9 @@ static int pn544_hci_i2c_probe(struct i2c_client *client,
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return -ENOMEM;
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}
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INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work);
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phy->fw_work_state = FW_WORK_STATE_IDLE;
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phy->i2c_dev = client;
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i2c_set_clientdata(client, phy);
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@ -428,7 +745,8 @@ static int pn544_hci_i2c_probe(struct i2c_client *client,
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r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME,
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PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM,
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PN544_HCI_I2C_LLC_MAX_PAYLOAD, NULL, &phy->hdev);
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PN544_HCI_I2C_LLC_MAX_PAYLOAD,
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pn544_hci_i2c_fw_download, &phy->hdev);
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if (r < 0)
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goto err_hci;
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@ -451,6 +769,10 @@ static int pn544_hci_i2c_remove(struct i2c_client *client)
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dev_dbg(&client->dev, "%s\n", __func__);
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cancel_work_sync(&phy->fw_work);
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if (phy->fw_work_state != FW_WORK_STATE_IDLE)
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pn544_hci_i2c_fw_work_complete(phy, -ENODEV);
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pn544_hci_remove(phy->hdev);
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if (phy->powered)
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