clock: mvebu new SoC changes for v3.15 (incremental pull #2)
- mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTIwnaAAoJEP45WPkGe8ZnqzcQALBc089kYIWoWK4aQanMxUPb o86G/p3bUYiOQOI/jLCDlaSxRPehQzSns/II1PgOjbRVCXi+6HEqrOy5yVhRW3JL 8RPaIdZvZlTYOxcF7Zelni2s/j1YPUbgfzXtawzNH9QdM+iQuSLMXCrStoIkJXUz rCcg2KBNNW5aBcmQtLcDgavdNtT/QCa524uGYQTR5YZNFQlL8a78GrqjkUkgD6e0 RH0guVmu5Wd5l7McHjq/mbcMg6gguPJI7Y3ddDjdB+02zAoKzlQ05HJLfDp6sybS 8e7DPYnA7TRJV2LG2jwsA5yGy3yrW5nmPBlfogZD7KlKl/pbTgEXyzf0OiP+OiDQ 7DGFAnSX7mDX3gRiwaac6YbyLCC6aVnPPsPzO/9zm5jy2c+u3BJjC6QHN4CVciYk OMyZzllrEJ3iGubFZb3I0smZcmopmoDyZMIz+abnqFi71jQmWZnjpjoE7qHJqSCe RObuI4V9w6kcJjhriPI8HRK2sMiQQwfZ+OGofffHiyWLJ/EtvruTyayO5IIjjVXE aDuHKa0z8s7sS/QDRyIFqr2N32T4mPczPaUvk4B3OmF6z1m5v3kKSYj4kzgZFOYx 3DwBdxKITxcWqlHuNU0lGmV2n75cTISH3NXCO3bIsC1ZQAKjzLRuqBzypxrHzE6m CyRu1U7m5LHo7yqSg4gv =tx7z -----END PGP SIGNATURE----- Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
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@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = nand (NAND clock)
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Required properties:
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- compatible : must be "marvell,armada-370-corediv-clock"
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- compatible : must be "marvell,armada-370-corediv-clock",
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"marvell,armada-375-corediv-clock",
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"marvell,armada-380-corediv-clock",
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- reg : must be the register address of Core Divider control register
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- #clock-cells : from common clock binding; shall be set to 1
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- clocks : must be set to the parent's phandle
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@ -204,6 +204,22 @@ static const struct clk_corediv_soc_desc armada370_corediv_soc = {
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.ratio_offset = 0x8,
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};
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static const struct clk_corediv_soc_desc armada380_corediv_soc = {
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.descs = mvebu_corediv_desc,
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.ndescs = ARRAY_SIZE(mvebu_corediv_desc),
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.ops = {
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.enable = clk_corediv_enable,
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.disable = clk_corediv_disable,
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.is_enabled = clk_corediv_is_enabled,
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.recalc_rate = clk_corediv_recalc_rate,
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.round_rate = clk_corediv_round_rate,
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.set_rate = clk_corediv_set_rate,
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},
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.ratio_reload = BIT(8),
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.enable_bit_offset = 16,
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.ratio_offset = 0x4,
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};
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static const struct clk_corediv_soc_desc armada375_corediv_soc = {
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.descs = mvebu_corediv_desc,
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.ndescs = ARRAY_SIZE(mvebu_corediv_desc),
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@ -213,7 +229,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
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.set_rate = clk_corediv_set_rate,
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},
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.ratio_reload = BIT(8),
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.ratio_offset = 0x8,
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.ratio_offset = 0x4,
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};
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static void __init
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@ -290,3 +306,10 @@ static void __init armada375_corediv_clk_init(struct device_node *node)
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}
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CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock",
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armada375_corediv_clk_init);
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static void __init armada380_corediv_clk_init(struct device_node *node)
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{
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return mvebu_corediv_clk_init(node, &armada380_corediv_soc);
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}
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CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
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armada380_corediv_clk_init);
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