irqchip/ath79-misc: Move the MISC driver from arch/mips/ath79/
The driver stays the same but the initialization changes a bit. For OF boards we now get the memory map from the OF node and use a linear mapping instead of the legacy mapping. For legacy boards we still use a legacy mapping and just pass down all the parameters from the board init code. Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.fr Signed-off-by: Jason Cooper <jason@lakedaemon.net>steinar/wifi_calib_4_9_kernel
Alban Bedel
Jason Cooper
parent
92e963f50f
commit
07ba4b061a
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@ -26,90 +26,6 @@
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#include "common.h"
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#include "machtypes.h"
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static void __init ath79_misc_intc_domain_init(
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struct device_node *node, int irq);
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static void ath79_misc_irq_handler(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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void __iomem *base = domain->host_data;
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u32 pending;
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pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(irq_linear_revmap(domain, bit));
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pending &= ~BIT(bit);
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}
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}
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static void ar71xx_misc_irq_unmask(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ath79_misc_irq_chip = {
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.name = "MISC",
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.irq_unmask = ar71xx_misc_irq_unmask,
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.irq_mask = ar71xx_misc_irq_mask,
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};
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static void __init ath79_misc_irq_init(void)
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{
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca955x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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ath79_misc_intc_domain_init(NULL, ATH79_CPU_IRQ(6));
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}
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static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
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{
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@ -248,69 +164,6 @@ asmlinkage void plat_irq_dispatch(void)
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}
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}
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static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops misc_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = misc_map,
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};
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static void __init ath79_misc_intc_domain_init(
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struct device_node *node, int irq)
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{
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void __iomem *base = ath79_reset_base;
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struct irq_domain *domain;
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domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
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ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, base);
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if (!domain)
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panic("Failed to add MISC irqdomain");
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/* Disable and clear all interrupts */
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
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}
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static int __init ath79_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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int irq;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq)
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panic("Failed to get MISC IRQ");
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ath79_misc_intc_domain_init(node, irq);
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return 0;
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}
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static int __init ar7100_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
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ar7100_misc_intc_of_init);
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static int __init ar7240_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
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ar7240_misc_intc_of_init);
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static int __init ar79_cpu_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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@ -348,6 +201,8 @@ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
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void __init arch_init_irq(void)
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{
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bool misc_is_ar71xx;
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if (mips_machtype == ATH79_MACH_GENERIC_OF) {
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irqchip_init();
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return;
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@ -362,7 +217,19 @@ void __init arch_init_irq(void)
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}
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mips_cpu_irq_init();
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ath79_misc_irq_init();
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if (soc_is_ar71xx() || soc_is_ar913x())
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misc_is_ar71xx = true;
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca955x())
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misc_is_ar71xx = false;
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else
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BUG();
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ath79_misc_irq_init(
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ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
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ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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@ -144,4 +144,7 @@ static inline u32 ath79_reset_rr(unsigned reg)
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void ath79_device_reset_set(u32 mask);
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void ath79_device_reset_clear(u32 mask);
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void ath79_misc_irq_init(void __iomem *regs, int irq,
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int irq_base, bool is_ar71xx);
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#endif /* __ASM_MACH_ATH79_H */
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@ -1,5 +1,6 @@
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obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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@ -0,0 +1,189 @@
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/*
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* Atheros AR71xx/AR724x/AR913x MISC interrupt controller
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*
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* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define AR71XX_RESET_REG_MISC_INT_STATUS 0
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#define AR71XX_RESET_REG_MISC_INT_ENABLE 4
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#define ATH79_MISC_IRQ_COUNT 32
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static void ath79_misc_irq_handler(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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void __iomem *base = domain->host_data;
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u32 pending;
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chained_irq_enter(chip, desc);
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pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (!pending) {
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spurious_interrupt();
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chained_irq_exit(chip, desc);
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return;
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}
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(irq_linear_revmap(domain, bit));
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pending &= ~BIT(bit);
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}
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chained_irq_exit(chip, desc);
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}
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static void ar71xx_misc_irq_unmask(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ath79_misc_irq_chip = {
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.name = "MISC",
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.irq_unmask = ar71xx_misc_irq_unmask,
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.irq_mask = ar71xx_misc_irq_mask,
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};
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static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops misc_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = misc_map,
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};
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static void __init ath79_misc_intc_domain_init(
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struct irq_domain *domain, int irq)
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{
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void __iomem *base = domain->host_data;
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/* Disable and clear all interrupts */
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
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}
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static int __init ath79_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *domain;
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void __iomem *base;
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int irq;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq) {
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pr_err("Failed to get MISC IRQ\n");
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return -EINVAL;
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}
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("Failed to get MISC IRQ registers\n");
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return -ENOMEM;
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}
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domain = irq_domain_add_linear(node, ATH79_MISC_IRQ_COUNT,
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&misc_irq_domain_ops, base);
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if (!domain) {
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pr_err("Failed to add MISC irqdomain\n");
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return -EINVAL;
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}
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ath79_misc_intc_domain_init(domain, irq);
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return 0;
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}
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static int __init ar7100_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
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ar7100_misc_intc_of_init);
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static int __init ar7240_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
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ar7240_misc_intc_of_init);
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void __init ath79_misc_irq_init(void __iomem *regs, int irq,
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int irq_base, bool is_ar71xx)
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{
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struct irq_domain *domain;
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if (is_ar71xx)
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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else
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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domain = irq_domain_add_legacy(NULL, ATH79_MISC_IRQ_COUNT,
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irq_base, 0, &misc_irq_domain_ops, regs);
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if (!domain)
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panic("Failed to create MISC irqdomain");
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ath79_misc_intc_domain_init(domain, irq);
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}
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