PCI: check szhi when sz is 0 when 64 bit iomem bigger than 4G
For pci mem resource that size is bigger than 4G, the sz returned by pc_size will be 0. So that resource is skipped, and register contained hi address will be treated as another 32bit resource. We need to use sz64 and pci_sz64 for 64 bit resource for clear logical. Typical usages for this: Opteron system with co-processor and the co-processor could take more than 4G RAM as pre-fetchable mem resource. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Cc: Andi Kleen <ak@suse.de> Cc: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -144,6 +144,32 @@ static u32 pci_size(u32 base, u32 maxbase, u32 mask)
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return size;
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}
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static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
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{
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u64 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static inline int is_64bit_memory(u32 mask)
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{
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if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
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return 1;
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return 0;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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unsigned int pos, reg, next;
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@ -151,6 +177,10 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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struct resource *res;
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for(pos=0; pos<howmany; pos = next) {
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u64 l64;
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u64 sz64;
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u32 raw_sz;
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next = pos+1;
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res = &dev->resource[pos];
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res->name = pci_name(dev);
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@ -163,9 +193,16 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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continue;
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if (l == 0xffffffff)
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l = 0;
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if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
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raw_sz = sz;
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if ((l & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) {
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sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
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if (!sz)
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/*
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* For 64bit prefetchable memory sz could be 0, if the
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* real size is bigger than 4G, so we need to check
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* szhi for that.
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*/
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if (!is_64bit_memory(l) && !sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
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@ -178,30 +215,36 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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}
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res->end = res->start + (unsigned long) sz;
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res->flags |= pci_calc_resource_flags(l);
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if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
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== (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
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if (is_64bit_memory(l)) {
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u32 szhi, lhi;
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pci_read_config_dword(dev, reg+4, &lhi);
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pci_write_config_dword(dev, reg+4, ~0);
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pci_read_config_dword(dev, reg+4, &szhi);
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pci_write_config_dword(dev, reg+4, lhi);
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szhi = pci_size(lhi, szhi, 0xffffffff);
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sz64 = ((u64)szhi << 32) | raw_sz;
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l64 = ((u64)lhi << 32) | l;
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sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
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next++;
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#if BITS_PER_LONG == 64
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res->start |= ((unsigned long) lhi) << 32;
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res->end = res->start + sz;
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if (szhi) {
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/* This BAR needs > 4GB? Wow. */
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res->end |= (unsigned long)szhi<<32;
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if (!sz64) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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continue;
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}
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res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
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res->end = res->start + sz64;
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#else
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if (szhi) {
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printk(KERN_ERR "PCI: Unable to handle 64-bit BAR for device %s\n", pci_name(dev));
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if (sz64 > 0x100000000ULL) {
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printk(KERN_ERR "PCI: Unable to handle 64-bit "
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"BAR for device %s\n", pci_name(dev));
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res->start = 0;
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res->flags = 0;
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} else if (lhi) {
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/* 64-bit wide address, treat as disabled */
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pci_write_config_dword(dev, reg, l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
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pci_write_config_dword(dev, reg,
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l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
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pci_write_config_dword(dev, reg+4, 0);
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res->start = 0;
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res->end = sz;
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