ARM: mm: improve do_ldrd_abort macro
Improve the do_ldrd_abort macro code - firstly, it inefficiently checks for the LDRD encoding by doing a multi-stage test of various bits. This can be simplified by generating a mask, bitmasking the instruction and then comparing the result. Secondly, we want to be able to test the result rather than branching to do_DataAbort, so remove the branch at the end and rename the macro to 'teq_ldrd' to reflect it's new usage. teq_ldrd macro returns 'eq' if the instruction was a LDRD. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -22,7 +22,8 @@ ENTRY(v5t_early_abort)
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r4] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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do_ldrd_abort tmp=ip, insn=r3
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teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
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beq do_DataAbort @ yes
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tst r3, #1 << 20 @ check write
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orreq r1, r1, #1 << 11
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b do_DataAbort
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@ -24,7 +24,8 @@ ENTRY(v5tj_early_abort)
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bne do_DataAbort
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r4] @ read aborted ARM instruction
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do_ldrd_abort tmp=ip, insn=r3
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teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
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beq do_DataAbort @ yes
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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b do_DataAbort
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@ -34,7 +34,8 @@ ENTRY(v6_early_abort)
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ldr r3, [r4] @ read aborted ARM instruction
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ARM_BE8(rev r3, r3)
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do_ldrd_abort tmp=ip, insn=r3
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teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
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beq do_DataAbort @ yes
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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#endif
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@ -29,12 +29,9 @@ not_thumb:
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* [7:4] == 1101
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* [20] == 0
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*/
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.macro do_ldrd_abort, tmp, insn
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tst \insn, #0x0e100000 @ [27:25,20] == 0
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bne not_ldrd
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and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
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cmp \tmp, #0x000000d0
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beq do_DataAbort
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not_ldrd:
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.macro teq_ldrd, tmp, insn
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mov \tmp, #0x0e100000
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orr \tmp, #0x000000f0
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and \tmp, \insn, \tmp
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teq \tmp, #0x000000d0
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.endm
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