ARM: pxa: add devicetree code for irq handling
Properly register on-chip interrupt using the irqdomain logic. The number of interrupts is taken from the devicetree node. That includes the following changes: - cpu_has_ipr() was converted from an inline function to a static bool variable, so it can be set using the "marvell,intc-priority" property inside the device node of the tree. - IRQ_BASE was converted from a macro to a runtime variable so that it can be initialized dynamically from the DT init code. - irq_base() now uses pxa_irq_base and just adds an offset. Hence, there are now no compile-time fixed values used in case of DT initialization. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>wifi-calibration
Daniel Mack
Haojian Zhuang
parent
9450be76d0
commit
089d03629b
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@ -17,6 +17,8 @@
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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@ -25,8 +27,6 @@
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#include "generic.h"
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#define IRQ_BASE io_p2v(0x40d00000)
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#define ICIP (0x000)
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#define ICMR (0x004)
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#define ICLR (0x008)
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@ -48,22 +48,19 @@
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* This is for peripheral IRQs internal to the PXA chip.
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*/
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static void __iomem *pxa_irq_base;
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static int pxa_internal_irq_nr;
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static inline int cpu_has_ipr(void)
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{
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return !cpu_is_pxa25x();
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}
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static bool cpu_has_ipr;
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static inline void __iomem *irq_base(int i)
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{
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static unsigned long phys_base[] = {
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0x40d00000,
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0x40d0009c,
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0x40d00130,
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static unsigned long phys_base_offset[] = {
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0x0,
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0x9c,
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0x130,
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};
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return io_p2v(phys_base[i]);
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return pxa_irq_base + phys_base_offset[i];
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}
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void pxa_mask_irq(struct irq_data *d)
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@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
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uint32_t icip, icmr, mask;
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do {
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icip = __raw_readl(IRQ_BASE + ICIP);
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icmr = __raw_readl(IRQ_BASE + ICMR);
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icip = __raw_readl(pxa_irq_base + ICIP);
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icmr = __raw_readl(pxa_irq_base + ICMR);
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mask = icip & icmr;
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if (mask == 0)
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@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
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BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
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pxa_internal_irq_nr = irq_nr;
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cpu_has_ipr = !cpu_is_pxa25x();
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pxa_irq_base = io_p2v(0x40d00000);
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for (n = 0; n < irq_nr; n += 32) {
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void __iomem *base = irq_base(n >> 5);
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@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
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__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
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for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
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/* initialize interrupt priority */
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if (cpu_has_ipr())
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__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
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if (cpu_has_ipr)
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__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
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irq = PXA_IRQ(i);
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irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
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@ -168,9 +167,9 @@ static int pxa_irq_suspend(void)
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__raw_writel(0, base + ICMR);
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}
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if (cpu_has_ipr()) {
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if (cpu_has_ipr) {
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for (i = 0; i < pxa_internal_irq_nr; i++)
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saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
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saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
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}
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return 0;
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@ -187,11 +186,11 @@ static void pxa_irq_resume(void)
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__raw_writel(0, base + ICLR);
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}
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if (cpu_has_ipr())
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if (cpu_has_ipr)
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for (i = 0; i < pxa_internal_irq_nr; i++)
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__raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
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__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
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__raw_writel(1, IRQ_BASE + ICCR);
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__raw_writel(1, pxa_irq_base + ICCR);
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}
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#else
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#define pxa_irq_suspend NULL
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@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = {
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.suspend = pxa_irq_suspend,
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.resume = pxa_irq_resume,
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};
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#ifdef CONFIG_OF
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static struct irq_domain *pxa_irq_domain;
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static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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void __iomem *base = irq_base(hw / 32);
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/* initialize interrupt priority */
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if (cpu_has_ipr)
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__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
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irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
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handle_level_irq);
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irq_set_chip_data(hw, base);
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set_irq_flags(hw, IRQF_VALID);
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return 0;
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}
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static struct irq_domain_ops pxa_irq_ops = {
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.map = pxa_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static const struct of_device_id intc_ids[] __initconst = {
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{ .compatible = "marvell,pxa-intc", },
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{}
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};
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void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
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{
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struct device_node *node;
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const struct of_device_id *of_id;
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struct pxa_intc_conf *conf;
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struct resource res;
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int n, ret;
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node = of_find_matching_node(NULL, intc_ids);
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if (!node) {
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pr_err("Failed to find interrupt controller in arch-pxa\n");
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return;
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}
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of_id = of_match_node(intc_ids, node);
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conf = of_id->data;
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ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
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&pxa_internal_irq_nr);
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if (ret) {
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pr_err("Not found marvell,intc-nr-irqs property\n");
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return;
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}
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ret = of_address_to_resource(node, 0, &res);
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if (ret < 0) {
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pr_err("No registers defined for node\n");
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return;
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}
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pxa_irq_base = io_p2v(res.start);
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if (of_find_property(node, "marvell,intc-priority", NULL))
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cpu_has_ipr = 1;
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ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
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if (ret < 0) {
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pr_err("Failed to allocate IRQ numbers\n");
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return;
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}
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pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
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&pxa_irq_ops, NULL);
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if (!pxa_irq_domain)
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panic("Unable to add PXA IRQ domain\n");
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irq_set_default_host(pxa_irq_domain);
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for (n = 0; n < pxa_internal_irq_nr; n += 32) {
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void __iomem *base = irq_base(n >> 5);
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__raw_writel(0, base + ICMR); /* disable all IRQs */
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__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
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}
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/* only unmasked interrupts kick us out of idle */
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__raw_writel(1, irq_base(0) + ICCR);
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pxa_internal_irq_chip.irq_set_wake = fn;
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}
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#endif /* CONFIG_OF */
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@ -40,6 +40,8 @@
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#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
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#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
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extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
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static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
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static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
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static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
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@ -382,7 +384,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
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pxa_ext_wakeup_chip.irq_set_wake = fn;
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}
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void __init pxa3xx_init_irq(void)
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static void __init __pxa3xx_init_irq(void)
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{
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/* enable CP6 access */
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u32 value;
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@ -390,10 +392,21 @@ void __init pxa3xx_init_irq(void)
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value |= (1 << 6);
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__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
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pxa_init_irq(56, pxa3xx_set_wake);
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pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
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}
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void __init pxa3xx_init_irq(void)
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{
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__pxa3xx_init_irq();
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pxa_init_irq(56, pxa3xx_set_wake);
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}
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void __init pxa3xx_dt_init_irq(void)
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{
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__pxa3xx_init_irq();
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pxa_dt_irq_init(pxa3xx_set_wake);
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}
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static struct map_desc pxa3xx_io_desc[] __initdata = {
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{ /* Mem Ctl */
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.virtual = (unsigned long)SMEMC_VIRT,
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