CRIS changes for 4.4
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEABECAAYFAlY3tC4ACgkQ31LbvUHyf1f/sgCeMpoZMTPgFTeBWCQDtp6zF6Fz 0YUAn22qMO9dlLVzKYaCoBWXd36tXnp3 =NVeF -----END PGP SIGNATURE----- Merge tag 'cris-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris Pull CRIS changes from Jesper Nilsson: "Mostly another batch of code removal due to move to standard frameworks for CRISv32, initial devicetree configuration for a couple of boards, and some small fixes for kgdb and time handling" * tag 'cris-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris: cris: Drop reference to get_cmos_time() CRIS: Drop code related to obsolete or unused kconfigs cris: time: Cleanup of persistent clock stuff cris: re-use helpers to dump data in hex format CRIS v32: remove old GPIO and LEDs code CRIS v32: remove I2C bitbanging driver CRIS v32: add ARTPEC-3 and P1343 device trees CRIS v32: dev88: add GPIO, LEDs, RTC, temp sensor CRIS: add dt-bindings symlink CRIS v32: increase NR_IRQS cris: arch-v10: kgdb: Add '__used' for static variable is_dyn_brkp cris: arch-v10: kgdb: Use BAR instead of DTP0 for register P12 cris: kgdb: use native hex2bin
This commit is contained in:
commit
0921f1efb6
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@ -57,7 +57,6 @@ config CRIS
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select ARCH_WANT_IPC_PARSE_VERSION
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select GENERIC_IRQ_SHOW
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select GENERIC_IOMAP
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select GENERIC_CMOS_UPDATE
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select MODULES_USE_ELF_RELA
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select CLONE_BACKWARDS2
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select OLD_SIGSUSPEND
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@ -354,63 +354,6 @@ no_command_line:
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blo 1b
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nop
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#ifdef CONFIG_BLK_DEV_ETRAXIDE
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;; disable ATA before enabling it in genconfig below
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moveq 0,$r0
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move.d $r0,[R_ATA_CTRL_DATA]
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move.d $r0,[R_ATA_TRANSFER_CNT]
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move.d $r0,[R_ATA_CONFIG]
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#if 0
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move.d R_PORT_G_DATA, $r1
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move.d $r0, [$r1]; assert ATA bus-reset
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nop
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nop
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nop
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nop
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nop
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nop
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move.d 0x08000000,$r0
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move.d $r0,[$r1]
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#endif
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#endif
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#ifdef CONFIG_JULIETTE
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;; configure external DMA channel 0 before enabling it in genconfig
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moveq 0,$r0
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move.d $r0,[R_EXT_DMA_0_ADDR]
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; cnt enable, word size, output, stop, size 0
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move.d IO_STATE (R_EXT_DMA_0_CMD, cnt, enable) \
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| IO_STATE (R_EXT_DMA_0_CMD, rqpol, ahigh) \
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| IO_STATE (R_EXT_DMA_0_CMD, apol, ahigh) \
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| IO_STATE (R_EXT_DMA_0_CMD, rq_ack, burst) \
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| IO_STATE (R_EXT_DMA_0_CMD, wid, word) \
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| IO_STATE (R_EXT_DMA_0_CMD, dir, output) \
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| IO_STATE (R_EXT_DMA_0_CMD, run, stop) \
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| IO_FIELD (R_EXT_DMA_0_CMD, trf_count, 0),$r0
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move.d $r0,[R_EXT_DMA_0_CMD]
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;; reset dma4 and wait for completion
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moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
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move.b $r0,[R_DMA_CH4_CMD]
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1: move.b [R_DMA_CH4_CMD],$r0
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and.b IO_MASK (R_DMA_CH4_CMD, cmd),$r0
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cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
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beq 1b
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nop
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;; reset dma5 and wait for completion
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moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
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move.b $r0,[R_DMA_CH5_CMD]
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1: move.b [R_DMA_CH5_CMD],$r0
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and.b IO_MASK (R_DMA_CH5_CMD, cmd),$r0
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cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
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beq 1b
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nop
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#endif
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;; Etrax product HW genconfig setup
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moveq 0,$r0
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@ -447,21 +390,6 @@ no_command_line:
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| IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0
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#endif
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G8_15_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0
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#endif
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G16_23_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0
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#endif
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G24_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0
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#endif
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move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
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move.d $r0,[R_GEN_CONFIG]
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@ -500,19 +428,9 @@ no_command_line:
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;; including their shadow registers
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move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
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or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0
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#endif
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move.b $r0,[port_pa_dir_shadow]
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move.b $r0,[R_PORT_PA_DIR]
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move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.b ~(1 << 7),$r0
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#else
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or.b (1 << 7),$r0
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#endif
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#endif
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move.b $r0,[port_pa_data_shadow]
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move.b $r0,[R_PORT_PA_DATA]
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@ -520,19 +438,9 @@ no_command_line:
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move.b $r0,[port_pb_config_shadow]
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move.b $r0,[R_PORT_PB_CONFIG]
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move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5)
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or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0
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#endif
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move.b $r0,[port_pb_dir_shadow]
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move.b $r0,[R_PORT_PB_DIR]
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move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.b ~(1 << 5),$r0
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#else
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or.b (1 << 5),$r0
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#endif
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#endif
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move.b $r0,[port_pb_data_shadow]
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move.b $r0,[R_PORT_PB_DATA]
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@ -541,20 +449,6 @@ no_command_line:
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move.d $r0, [R_PORT_PB_I2C]
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moveq 0,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G10)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.d ~(1 << 10),$r0
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#else
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or.d (1 << 10),$r0
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#endif
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#endif
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G11)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.d ~(1 << 11),$r0
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#else
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or.d (1 << 11),$r0
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#endif
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#endif
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move.d $r0,[port_g_data_shadow]
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move.d $r0,[R_PORT_G_DATA]
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@ -275,7 +275,7 @@ static char remcomOutBuffer[BUFMAX];
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/* Error and warning messages. */
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enum error_type
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{
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SUCCESS, E01, E02, E03, E04, E05, E06, E07
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SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
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};
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static char *error_message[] =
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{
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@ -286,7 +286,8 @@ static char *error_message[] =
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"E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
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"E05 Change register content - P - the register is not implemented..",
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"E06 Change memory content - M - internal error.",
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"E07 Change register content - P - the register is not stored on the stack"
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"E07 Change register content - P - the register is not stored on the stack",
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"E08 Invalid parameter"
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};
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/********************************* Register image ****************************/
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/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's
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@ -351,7 +352,7 @@ char internal_stack[INTERNAL_STACK_SIZE];
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breakpoint to be handled. A static breakpoint uses the content of register
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BRP as it is whereas a dynamic breakpoint requires subtraction with 2
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in order to execute the instruction. The first breakpoint is static. */
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static unsigned char is_dyn_brkp = 0;
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static unsigned char __used is_dyn_brkp;
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/********************************* String library ****************************/
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/* Single-step over library functions creates trap loops. */
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@ -413,18 +414,6 @@ gdb_cris_strtol (const char *s, char **endptr, int base)
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}
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/********************************** Packet I/O ******************************/
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/* Returns the integer equivalent of a hexadecimal character. */
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static int
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hex (char ch)
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{
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if ((ch >= 'a') && (ch <= 'f'))
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return (ch - 'a' + 10);
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if ((ch >= '0') && (ch <= '9'))
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return (ch - '0');
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if ((ch >= 'A') && (ch <= 'F'))
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return (ch - 'A' + 10);
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return (-1);
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}
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/* Convert the memory, pointed to by mem into hexadecimal representation.
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Put the result in buf, and return a pointer to the last character
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@ -455,22 +444,6 @@ mem2hex(char *buf, unsigned char *mem, int count)
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return (buf);
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}
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/* Convert the array, in hexadecimal representation, pointed to by buf into
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binary representation. Put the result in mem, and return a pointer to
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the character after the last byte written. */
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static unsigned char*
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hex2mem (unsigned char *mem, char *buf, int count)
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{
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int i;
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unsigned char ch;
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for (i = 0; i < count; i++) {
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ch = hex (*buf++) << 4;
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ch = ch + hex (*buf++);
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*mem++ = ch;
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}
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return (mem);
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}
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/* Put the content of the array, in binary representation, pointed to by buf
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into memory pointed to by mem, and return a pointer to the character after
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the last byte written.
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@ -524,8 +497,8 @@ getpacket (char *buffer)
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buffer[count] = '\0';
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if (ch == '#') {
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xmitcsum = hex (getDebugChar ()) << 4;
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xmitcsum += hex (getDebugChar ());
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xmitcsum = hex_to_bin(getDebugChar()) << 4;
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xmitcsum += hex_to_bin(getDebugChar());
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if (checksum != xmitcsum) {
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/* Wrong checksum */
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putDebugChar ('-');
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@ -599,7 +572,7 @@ putDebugString (const unsigned char *str, int length)
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/********************************* Register image ****************************/
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/* Write a value to a specified register in the register image of the current
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thread. Returns status code SUCCESS, E02 or E05. */
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thread. Returns status code SUCCESS, E02, E05 or E08. */
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static int
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write_register (int regno, char *val)
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{
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@ -608,8 +581,9 @@ write_register (int regno, char *val)
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if (regno >= R0 && regno <= PC) {
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/* 32-bit register with simple offset. */
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hex2mem ((unsigned char *)current_reg + regno * sizeof(unsigned int),
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val, sizeof(unsigned int));
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if (hex2bin((unsigned char *)current_reg + regno * sizeof(unsigned int),
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val, sizeof(unsigned int)))
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status = E08;
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}
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else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
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/* Do not support read-only registers. */
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@ -618,13 +592,15 @@ write_register (int regno, char *val)
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else if (regno == CCR) {
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/* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented,
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and P7 (MOF) is 32 bits in ETRAX 100LX. */
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hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
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val, sizeof(unsigned short));
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if (hex2bin((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
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val, sizeof(unsigned short)))
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status = E08;
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}
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else if (regno >= MOF && regno <= USP) {
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/* 32 bit register with complex offset. (P8 has been taken care of.) */
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hex2mem ((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
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val, sizeof(unsigned int));
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if (hex2bin((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
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val, sizeof(unsigned int)))
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status = E08;
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}
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else {
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/* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
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@ -759,9 +735,11 @@ handle_exception (int sigval)
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/* Write registers. GXX..XX
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Each byte of register data is described by two hex digits.
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Success: OK
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Failure: void. */
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hex2mem((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers));
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gdb_cris_strcpy (remcomOutBuffer, "OK");
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Failure: E08. */
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if (hex2bin((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers)))
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gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
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else
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gdb_cris_strcpy (remcomOutBuffer, "OK");
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break;
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case 'P':
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@ -771,7 +749,7 @@ handle_exception (int sigval)
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for each byte in the register (target byte order). P1f=11223344 means
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set register 31 to 44332211.
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Success: OK
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Failure: E02, E05 */
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Failure: E02, E05, E08 */
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{
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char *suffix;
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int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16);
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|
@ -791,6 +769,10 @@ handle_exception (int sigval)
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/* Do not support non-existing registers on the stack. */
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gdb_cris_strcpy (remcomOutBuffer, error_message[E07]);
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break;
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case E08:
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/* Invalid parameter. */
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gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
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break;
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default:
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||||
/* Valid register number. */
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gdb_cris_strcpy (remcomOutBuffer, "OK");
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|
@ -826,7 +808,7 @@ handle_exception (int sigval)
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AA..AA is the start address, LLLL is the number of bytes, and
|
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XX..XX is the hexadecimal data.
|
||||
Success: OK
|
||||
Failure: void. */
|
||||
Failure: E08. */
|
||||
{
|
||||
char *lenptr;
|
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char *dataptr;
|
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|
@ -835,14 +817,15 @@ handle_exception (int sigval)
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int length = gdb_cris_strtol(lenptr+1, &dataptr, 16);
|
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if (*lenptr == ',' && *dataptr == ':') {
|
||||
if (remcomInBuffer[0] == 'M') {
|
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hex2mem(addr, dataptr + 1, length);
|
||||
}
|
||||
else /* X */ {
|
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if (hex2bin(addr, dataptr + 1, length))
|
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gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
|
||||
else
|
||||
gdb_cris_strcpy (remcomOutBuffer, "OK");
|
||||
} else /* X */ {
|
||||
bin2mem(addr, dataptr + 1, length);
|
||||
gdb_cris_strcpy (remcomOutBuffer, "OK");
|
||||
}
|
||||
gdb_cris_strcpy (remcomOutBuffer, "OK");
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
gdb_cris_strcpy (remcomOutBuffer, error_message[E06]);
|
||||
}
|
||||
}
|
||||
|
@ -970,7 +953,7 @@ asm ("\n"
|
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" move $ibr,[cris_reg+0x4E] ; P9,\n"
|
||||
" move $irp,[cris_reg+0x52] ; P10,\n"
|
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" move $srp,[cris_reg+0x56] ; P11,\n"
|
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" move $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n"
|
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" move $bar,[cris_reg+0x5A] ; P12,\n"
|
||||
" ; P13, register DCCR already saved\n"
|
||||
";; Due to the old assembler-versions BRP might not be recognized\n"
|
||||
" .word 0xE670 ; move brp,r0\n"
|
||||
|
@ -1063,7 +1046,7 @@ asm ("\n"
|
|||
" move $ibr,[cris_reg+0x4E] ; P9,\n"
|
||||
" move $irp,[cris_reg+0x52] ; P10,\n"
|
||||
" move $srp,[cris_reg+0x56] ; P11,\n"
|
||||
" move $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n"
|
||||
" move $bar,[cris_reg+0x5A] ; P12,\n"
|
||||
" ; P13, register DCCR already saved\n"
|
||||
";; Due to the old assembler-versions BRP might not be recognized\n"
|
||||
" .word 0xE670 ; move brp,r0\n"
|
||||
|
|
|
@ -68,14 +68,10 @@ paging_init(void)
|
|||
|
||||
*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
|
||||
IO_STATE(R_MMU_KSEG, seg_e, page ) |
|
||||
IO_STATE(R_MMU_KSEG, seg_d, page ) |
|
||||
IO_STATE(R_MMU_KSEG, seg_c, page ) |
|
||||
IO_STATE(R_MMU_KSEG, seg_d, page ) |
|
||||
IO_STATE(R_MMU_KSEG, seg_c, page ) |
|
||||
IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
|
||||
#ifdef CONFIG_JULIETTE
|
||||
IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */
|
||||
#else
|
||||
IO_STATE(R_MMU_KSEG, seg_a, page ) |
|
||||
#endif
|
||||
IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
|
||||
IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
|
||||
IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
|
||||
|
@ -92,14 +88,10 @@ paging_init(void)
|
|||
IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
|
||||
#ifdef CONFIG_JULIETTE
|
||||
IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) |
|
||||
#else
|
||||
IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
|
||||
#endif
|
||||
IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
|
||||
IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
|
||||
|
||||
|
||||
*R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
|
||||
|
|
|
@ -10,95 +10,6 @@ config ETRAX_DRAM_VIRTUAL_BASE
|
|||
depends on ETRAX_ARCH_V32
|
||||
default "c0000000"
|
||||
|
||||
choice
|
||||
prompt "Nbr of Ethernet LED groups"
|
||||
depends on ETRAX_ARCH_V32
|
||||
default ETRAX_NBR_LED_GRP_ONE
|
||||
help
|
||||
Select how many Ethernet LED groups that can be used. Usually one per Ethernet
|
||||
interface is a good choice.
|
||||
|
||||
config ETRAX_NBR_LED_GRP_ZERO
|
||||
bool "Use zero LED groups"
|
||||
help
|
||||
Select this if you do not want any Ethernet LEDs.
|
||||
|
||||
config ETRAX_NBR_LED_GRP_ONE
|
||||
bool "Use one LED group"
|
||||
help
|
||||
Select this if you want one Ethernet LED group. This LED group
|
||||
can be used for one or more Ethernet interfaces. However, it is
|
||||
recommended that each Ethernet interface use a dedicated LED group.
|
||||
|
||||
config ETRAX_NBR_LED_GRP_TWO
|
||||
bool "Use two LED groups"
|
||||
help
|
||||
Select this if you want two Ethernet LED groups. This is the
|
||||
best choice if you have more than one Ethernet interface and
|
||||
would like to have separate LEDs for the interfaces.
|
||||
|
||||
endchoice
|
||||
|
||||
config ETRAX_LED_G_NET0
|
||||
string "Ethernet LED group 0 green LED bit"
|
||||
depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
|
||||
default "PA3"
|
||||
help
|
||||
Bit to use for the green LED in Ethernet LED group 0.
|
||||
|
||||
config ETRAX_LED_R_NET0
|
||||
string "Ethernet LED group 0 red LED bit"
|
||||
depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
|
||||
default "PA4"
|
||||
help
|
||||
Bit to use for the red LED in Ethernet LED group 0.
|
||||
|
||||
config ETRAX_LED_G_NET1
|
||||
string "Ethernet group 1 green LED bit"
|
||||
depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
|
||||
default ""
|
||||
help
|
||||
Bit to use for the green LED in Ethernet LED group 1.
|
||||
|
||||
config ETRAX_LED_R_NET1
|
||||
string "Ethernet group 1 red LED bit"
|
||||
depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
|
||||
default ""
|
||||
help
|
||||
Bit to use for the red LED in Ethernet LED group 1.
|
||||
|
||||
config ETRAX_V32_LED2G
|
||||
string "Second green LED bit"
|
||||
depends on ETRAX_ARCH_V32
|
||||
default "PA5"
|
||||
help
|
||||
Bit to use for the first green LED (status LED).
|
||||
Most Axis products use bit A5 here.
|
||||
|
||||
config ETRAX_V32_LED2R
|
||||
string "Second red LED bit"
|
||||
depends on ETRAX_ARCH_V32
|
||||
default "PA6"
|
||||
help
|
||||
Bit to use for the first red LED (network LED).
|
||||
Most Axis products use bit A6 here.
|
||||
|
||||
config ETRAX_V32_LED3G
|
||||
string "Third green LED bit"
|
||||
depends on ETRAX_ARCH_V32
|
||||
default "PA7"
|
||||
help
|
||||
Bit to use for the first green LED (drive/power LED).
|
||||
Most Axis products use bit A7 here.
|
||||
|
||||
config ETRAX_V32_LED3R
|
||||
string "Third red LED bit"
|
||||
depends on ETRAX_ARCH_V32
|
||||
default "PA7"
|
||||
help
|
||||
Bit to use for the first red LED (drive/power LED).
|
||||
Most Axis products use bit A7 here.
|
||||
|
||||
choice
|
||||
prompt "Kernel GDB port"
|
||||
depends on ETRAX_KGDB
|
||||
|
|
|
@ -149,173 +149,6 @@ config ETRAX_NANDBOOT
|
|||
Say Y if your boot code, kernel and root file system is in
|
||||
NAND flash. Say N if they are in NOR flash.
|
||||
|
||||
config ETRAX_I2C
|
||||
bool "I2C driver"
|
||||
depends on ETRAX_ARCH_V32
|
||||
help
|
||||
This option enables the I2C driver used by e.g. the RTC driver.
|
||||
|
||||
config ETRAX_V32_I2C_DATA_PORT
|
||||
string "I2C data pin"
|
||||
depends on ETRAX_I2C
|
||||
help
|
||||
The pin to use for I2C data.
|
||||
|
||||
config ETRAX_V32_I2C_CLK_PORT
|
||||
string "I2C clock pin"
|
||||
depends on ETRAX_I2C
|
||||
help
|
||||
The pin to use for I2C clock.
|
||||
|
||||
config ETRAX_GPIO
|
||||
bool "GPIO support"
|
||||
depends on ETRAX_ARCH_V32
|
||||
---help---
|
||||
Enables the ETRAX general port device (major 120, minors 0-4).
|
||||
You can use this driver to access the general port bits. It supports
|
||||
these ioctl's:
|
||||
#include <linux/etraxgpio.h>
|
||||
fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
|
||||
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
|
||||
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
|
||||
err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val);
|
||||
Remember that you need to setup the port directions appropriately in
|
||||
the General configuration.
|
||||
|
||||
config ETRAX_VIRTUAL_GPIO
|
||||
bool "Virtual GPIO support"
|
||||
depends on ETRAX_GPIO
|
||||
help
|
||||
Enables the virtual Etrax general port device (major 120, minor 6).
|
||||
It uses an I/O expander for the I2C-bus.
|
||||
|
||||
config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
|
||||
int "Virtual GPIO interrupt pin on PA pin"
|
||||
range 0 7
|
||||
depends on ETRAX_VIRTUAL_GPIO
|
||||
help
|
||||
The pin to use on PA for virtual gpio interrupt.
|
||||
|
||||
config ETRAX_PA_CHANGEABLE_DIR
|
||||
hex "PA user changeable dir mask"
|
||||
depends on ETRAX_GPIO
|
||||
default "0x00" if ETRAXFS
|
||||
default "0x00000000" if !ETRAXFS
|
||||
help
|
||||
This is a bitmask with information of what bits in PA that a
|
||||
user can change direction on using ioctl's.
|
||||
Bit set = changeable.
|
||||
You probably want 0 here, but it depends on your hardware.
|
||||
|
||||
config ETRAX_PA_CHANGEABLE_BITS
|
||||
hex "PA user changeable bits mask"
|
||||
depends on ETRAX_GPIO
|
||||
default "0x00" if ETRAXFS
|
||||
default "0x00000000" if !ETRAXFS
|
||||
help
|
||||
This is a bitmask with information of what bits in PA
|
||||
that a user can change the value on using ioctl's.
|
||||
Bit set = changeable.
|
||||
|
||||
config ETRAX_PB_CHANGEABLE_DIR
|
||||
hex "PB user changeable dir mask"
|
||||
depends on ETRAX_GPIO
|
||||
default "0x00000" if ETRAXFS
|
||||
default "0x00000000" if !ETRAXFS
|
||||
help
|
||||
This is a bitmask with information of what bits in PB
|
||||
that a user can change direction on using ioctl's.
|
||||
Bit set = changeable.
|
||||
You probably want 0 here, but it depends on your hardware.
|
||||
|
||||
config ETRAX_PB_CHANGEABLE_BITS
|
||||
hex "PB user changeable bits mask"
|
||||
depends on ETRAX_GPIO
|
||||
default "0x00000" if ETRAXFS
|
||||
default "0x00000000" if !ETRAXFS
|
||||
help
|
||||
This is a bitmask with information of what bits in PB
|
||||
that a user can change the value on using ioctl's.
|
||||
Bit set = changeable.
|
||||
|
||||
config ETRAX_PC_CHANGEABLE_DIR
|
||||
hex "PC user changeable dir mask"
|
||||
depends on ETRAX_GPIO
|
||||
default "0x00000" if ETRAXFS
|
||||
default "0x00000000" if !ETRAXFS
|
||||
help
|
||||
This is a bitmask with information of what bits in PC
|
||||
that a user can change direction on using ioctl's.
|
||||
Bit set = changeable.
|
||||
You probably want 0 here, but it depends on your hardware.
|
||||
|
||||
config ETRAX_PC_CHANGEABLE_BITS
|
||||
hex "PC user changeable bits mask"
|
||||
depends on ETRAX_GPIO
|
||||
default "0x00000" if ETRAXFS
|
||||
default "0x00000000" if !ETRAXFS
|
||||
help
|
||||
This is a bitmask with information of what bits in PC
|
||||
that a user can change the value on using ioctl's.
|
||||
Bit set = changeable.
|
||||
|
||||
config ETRAX_PD_CHANGEABLE_DIR
|
||||
hex "PD user changeable dir mask"
|
||||
depends on ETRAX_GPIO && ETRAXFS
|
||||
default "0x00000"
|
||||
help
|
||||
This is a bitmask with information of what bits in PD
|
||||
that a user can change direction on using ioctl's.
|
||||
Bit set = changeable.
|
||||
You probably want 0x00000 here, but it depends on your hardware.
|
||||
|
||||
config ETRAX_PD_CHANGEABLE_BITS
|
||||
hex "PD user changeable bits mask"
|
||||
depends on ETRAX_GPIO && ETRAXFS
|
||||
default "0x00000"
|
||||
help
|
||||
This is a bitmask (18 bits) with information of what bits in PD
|
||||
that a user can change the value on using ioctl's.
|
||||
Bit set = changeable.
|
||||
|
||||
config ETRAX_PE_CHANGEABLE_DIR
|
||||
hex "PE user changeable dir mask"
|
||||
depends on ETRAX_GPIO && ETRAXFS
|
||||
default "0x00000"
|
||||
help
|
||||
This is a bitmask (18 bits) with information of what bits in PE
|
||||
that a user can change direction on using ioctl's.
|
||||
Bit set = changeable.
|
||||
You probably want 0x00000 here, but it depends on your hardware.
|
||||
|
||||
config ETRAX_PE_CHANGEABLE_BITS
|
||||
hex "PE user changeable bits mask"
|
||||
depends on ETRAX_GPIO && ETRAXFS
|
||||
default "0x00000"
|
||||
help
|
||||
This is a bitmask (18 bits) with information of what bits in PE
|
||||
that a user can change the value on using ioctl's.
|
||||
Bit set = changeable.
|
||||
|
||||
config ETRAX_PV_CHANGEABLE_DIR
|
||||
hex "PV user changeable dir mask"
|
||||
depends on ETRAX_VIRTUAL_GPIO
|
||||
default "0x0000"
|
||||
help
|
||||
This is a bitmask (16 bits) with information of what bits in PV
|
||||
that a user can change direction on using ioctl's.
|
||||
Bit set = changeable.
|
||||
You probably want 0x0000 here, but it depends on your hardware.
|
||||
|
||||
config ETRAX_PV_CHANGEABLE_BITS
|
||||
hex "PV user changeable bits mask"
|
||||
depends on ETRAX_VIRTUAL_GPIO
|
||||
default "0x0000"
|
||||
help
|
||||
This is a bitmask (16 bits) with information of what bits in PV
|
||||
that a user can change the value on using ioctl's.
|
||||
Bit set = changeable.
|
||||
|
||||
config ETRAX_CARDBUS
|
||||
bool "Cardbus support"
|
||||
depends on ETRAX_ARCH_V32
|
||||
|
|
|
@ -7,6 +7,5 @@ obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
|
|||
obj-$(CONFIG_ETRAXFS) += mach-fs/
|
||||
obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/
|
||||
obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o
|
||||
obj-$(CONFIG_ETRAX_I2C) += i2c.o
|
||||
obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
|
||||
obj-$(CONFIG_PCI) += pci/
|
||||
|
|
|
@ -361,7 +361,7 @@ static int __init init_axis_flash(void)
|
|||
|
||||
#if 0 /* Dump flash memory so we can see what is going on */
|
||||
if (main_mtd) {
|
||||
int sectoraddr, i;
|
||||
int sectoraddr;
|
||||
for (sectoraddr = 0; sectoraddr < 2*65536+4096;
|
||||
sectoraddr += PAGESIZE) {
|
||||
main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len,
|
||||
|
@ -369,21 +369,7 @@ static int __init init_axis_flash(void)
|
|||
printk(KERN_INFO
|
||||
"Sector at %d (length %d):\n",
|
||||
sectoraddr, len);
|
||||
for (i = 0; i < PAGESIZE; i += 16) {
|
||||
printk(KERN_INFO
|
||||
"%02x %02x %02x %02x "
|
||||
"%02x %02x %02x %02x "
|
||||
"%02x %02x %02x %02x "
|
||||
"%02x %02x %02x %02x\n",
|
||||
page[i] & 255, page[i+1] & 255,
|
||||
page[i+2] & 255, page[i+3] & 255,
|
||||
page[i+4] & 255, page[i+5] & 255,
|
||||
page[i+6] & 255, page[i+7] & 255,
|
||||
page[i+8] & 255, page[i+9] & 255,
|
||||
page[i+10] & 255, page[i+11] & 255,
|
||||
page[i+12] & 255, page[i+13] & 255,
|
||||
page[i+14] & 255, page[i+15] & 255);
|
||||
}
|
||||
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, page, PAGESIZE, false);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
@ -417,25 +403,11 @@ static int __init init_axis_flash(void)
|
|||
|
||||
#if 0 /* Dump partition table so we can see what is going on */
|
||||
printk(KERN_INFO
|
||||
"axisflashmap: flash read %d bytes at 0x%08x, data: "
|
||||
"%02x %02x %02x %02x %02x %02x %02x %02x\n",
|
||||
len, CONFIG_ETRAX_PTABLE_SECTOR,
|
||||
page[0] & 255, page[1] & 255,
|
||||
page[2] & 255, page[3] & 255,
|
||||
page[4] & 255, page[5] & 255,
|
||||
page[6] & 255, page[7] & 255);
|
||||
"axisflashmap: flash read %d bytes at 0x%08x, data: %8ph\n",
|
||||
len, CONFIG_ETRAX_PTABLE_SECTOR, page);
|
||||
printk(KERN_INFO
|
||||
"axisflashmap: partition table offset %d, data: "
|
||||
"%02x %02x %02x %02x %02x %02x %02x %02x\n",
|
||||
PARTITION_TABLE_OFFSET,
|
||||
page[PARTITION_TABLE_OFFSET+0] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+1] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+2] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+3] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+4] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+5] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+6] & 255,
|
||||
page[PARTITION_TABLE_OFFSET+7] & 255);
|
||||
"axisflashmap: partition table offset %d, data: %8ph\n",
|
||||
PARTITION_TABLE_OFFSET, page + PARTITION_TABLE_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -1,751 +0,0 @@
|
|||
/*!***************************************************************************
|
||||
*!
|
||||
*! FILE NAME : i2c.c
|
||||
*!
|
||||
*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other
|
||||
*! kernel modules (i2c_writereg/readreg) and from userspace using
|
||||
*! ioctl()'s
|
||||
*!
|
||||
*! Nov 30 1998 Torbjorn Eliasson Initial version.
|
||||
*! Bjorn Wesen Elinux kernel version.
|
||||
*! Jan 14 2000 Johan Adolfsson Fixed PB shadow register stuff -
|
||||
*! don't use PB_I2C if DS1302 uses same bits,
|
||||
*! use PB.
|
||||
*| June 23 2003 Pieter Grimmerink Added 'i2c_sendnack'. i2c_readreg now
|
||||
*| generates nack on last received byte,
|
||||
*| instead of ack.
|
||||
*| i2c_getack changed data level while clock
|
||||
*| was high, causing DS75 to see a stop condition
|
||||
*!
|
||||
*! ---------------------------------------------------------------------------
|
||||
*!
|
||||
*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN
|
||||
*!
|
||||
*!***************************************************************************/
|
||||
|
||||
/****************** INCLUDE FILES SECTION ***********************************/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#include <asm/etraxi2c.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
#include "i2c.h"
|
||||
|
||||
/****************** I2C DEFINITION SECTION *************************/
|
||||
|
||||
#define D(x)
|
||||
|
||||
#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */
|
||||
static DEFINE_MUTEX(i2c_mutex);
|
||||
static const char i2c_name[] = "i2c";
|
||||
|
||||
#define CLOCK_LOW_TIME 8
|
||||
#define CLOCK_HIGH_TIME 8
|
||||
#define START_CONDITION_HOLD_TIME 8
|
||||
#define STOP_CONDITION_HOLD_TIME 8
|
||||
#define ENABLE_OUTPUT 0x01
|
||||
#define ENABLE_INPUT 0x00
|
||||
#define I2C_CLOCK_HIGH 1
|
||||
#define I2C_CLOCK_LOW 0
|
||||
#define I2C_DATA_HIGH 1
|
||||
#define I2C_DATA_LOW 0
|
||||
|
||||
#define i2c_enable()
|
||||
#define i2c_disable()
|
||||
|
||||
/* enable or disable output-enable, to select output or input on the i2c bus */
|
||||
|
||||
#define i2c_dir_out() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_out)
|
||||
#define i2c_dir_in() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_in)
|
||||
|
||||
/* control the i2c clock and data signals */
|
||||
|
||||
#define i2c_clk(x) crisv32_io_set(&cris_i2c_clk, x)
|
||||
#define i2c_data(x) crisv32_io_set(&cris_i2c_data, x)
|
||||
|
||||
/* read a bit from the i2c interface */
|
||||
|
||||
#define i2c_getbit() crisv32_io_rd(&cris_i2c_data)
|
||||
|
||||
#define i2c_delay(usecs) udelay(usecs)
|
||||
|
||||
static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */
|
||||
|
||||
/****************** VARIABLE SECTION ************************************/
|
||||
|
||||
static struct crisv32_iopin cris_i2c_clk;
|
||||
static struct crisv32_iopin cris_i2c_data;
|
||||
|
||||
/****************** FUNCTION DEFINITION SECTION *************************/
|
||||
|
||||
|
||||
/* generate i2c start condition */
|
||||
|
||||
void
|
||||
i2c_start(void)
|
||||
{
|
||||
/*
|
||||
* SCL=1 SDA=1
|
||||
*/
|
||||
i2c_dir_out();
|
||||
i2c_delay(CLOCK_HIGH_TIME/6);
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME);
|
||||
/*
|
||||
* SCL=1 SDA=0
|
||||
*/
|
||||
i2c_data(I2C_DATA_LOW);
|
||||
i2c_delay(START_CONDITION_HOLD_TIME);
|
||||
/*
|
||||
* SCL=0 SDA=0
|
||||
*/
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
}
|
||||
|
||||
/* generate i2c stop condition */
|
||||
|
||||
void
|
||||
i2c_stop(void)
|
||||
{
|
||||
i2c_dir_out();
|
||||
|
||||
/*
|
||||
* SCL=0 SDA=0
|
||||
*/
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_data(I2C_DATA_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME*2);
|
||||
/*
|
||||
* SCL=1 SDA=0
|
||||
*/
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME*2);
|
||||
/*
|
||||
* SCL=1 SDA=1
|
||||
*/
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
i2c_delay(STOP_CONDITION_HOLD_TIME);
|
||||
|
||||
i2c_dir_in();
|
||||
}
|
||||
|
||||
/* write a byte to the i2c interface */
|
||||
|
||||
void
|
||||
i2c_outbyte(unsigned char x)
|
||||
{
|
||||
int i;
|
||||
|
||||
i2c_dir_out();
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (x & 0x80) {
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
} else {
|
||||
i2c_data(I2C_DATA_LOW);
|
||||
}
|
||||
|
||||
i2c_delay(CLOCK_LOW_TIME/2);
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME);
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME/2);
|
||||
x <<= 1;
|
||||
}
|
||||
i2c_data(I2C_DATA_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME/2);
|
||||
|
||||
/*
|
||||
* enable input
|
||||
*/
|
||||
i2c_dir_in();
|
||||
}
|
||||
|
||||
/* read a byte from the i2c interface */
|
||||
|
||||
unsigned char
|
||||
i2c_inbyte(void)
|
||||
{
|
||||
unsigned char aBitByte = 0;
|
||||
int i;
|
||||
|
||||
/* Switch off I2C to get bit */
|
||||
i2c_disable();
|
||||
i2c_dir_in();
|
||||
i2c_delay(CLOCK_HIGH_TIME/2);
|
||||
|
||||
/* Get bit */
|
||||
aBitByte |= i2c_getbit();
|
||||
|
||||
/* Enable I2C */
|
||||
i2c_enable();
|
||||
i2c_delay(CLOCK_LOW_TIME/2);
|
||||
|
||||
for (i = 1; i < 8; i++) {
|
||||
aBitByte <<= 1;
|
||||
/* Clock pulse */
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME);
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
|
||||
/* Switch off I2C to get bit */
|
||||
i2c_disable();
|
||||
i2c_dir_in();
|
||||
i2c_delay(CLOCK_HIGH_TIME/2);
|
||||
|
||||
/* Get bit */
|
||||
aBitByte |= i2c_getbit();
|
||||
|
||||
/* Enable I2C */
|
||||
i2c_enable();
|
||||
i2c_delay(CLOCK_LOW_TIME/2);
|
||||
}
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME);
|
||||
|
||||
/*
|
||||
* we leave the clock low, getbyte is usually followed
|
||||
* by sendack/nack, they assume the clock to be low
|
||||
*/
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
return aBitByte;
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: i2c_getack
|
||||
*#
|
||||
*# DESCRIPTION : checks if ack was received from ic2
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
|
||||
int
|
||||
i2c_getack(void)
|
||||
{
|
||||
int ack = 1;
|
||||
/*
|
||||
* enable output
|
||||
*/
|
||||
i2c_dir_out();
|
||||
/*
|
||||
* Release data bus by setting
|
||||
* data high
|
||||
*/
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
/*
|
||||
* enable input
|
||||
*/
|
||||
i2c_dir_in();
|
||||
i2c_delay(CLOCK_HIGH_TIME/4);
|
||||
/*
|
||||
* generate ACK clock pulse
|
||||
*/
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
#if 0
|
||||
/*
|
||||
* Use PORT PB instead of I2C
|
||||
* for input. (I2C not working)
|
||||
*/
|
||||
i2c_clk(1);
|
||||
i2c_data(1);
|
||||
/*
|
||||
* switch off I2C
|
||||
*/
|
||||
i2c_data(1);
|
||||
i2c_disable();
|
||||
i2c_dir_in();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* now wait for ack
|
||||
*/
|
||||
i2c_delay(CLOCK_HIGH_TIME/2);
|
||||
/*
|
||||
* check for ack
|
||||
*/
|
||||
if (i2c_getbit())
|
||||
ack = 0;
|
||||
i2c_delay(CLOCK_HIGH_TIME/2);
|
||||
if (!ack) {
|
||||
if (!i2c_getbit()) /* receiver pulld SDA low */
|
||||
ack = 1;
|
||||
i2c_delay(CLOCK_HIGH_TIME/2);
|
||||
}
|
||||
|
||||
/*
|
||||
* our clock is high now, make sure data is low
|
||||
* before we enable our output. If we keep data high
|
||||
* and enable output, we would generate a stop condition.
|
||||
*/
|
||||
#if 0
|
||||
i2c_data(I2C_DATA_LOW);
|
||||
|
||||
/*
|
||||
* end clock pulse
|
||||
*/
|
||||
i2c_enable();
|
||||
i2c_dir_out();
|
||||
#endif
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_delay(CLOCK_HIGH_TIME/4);
|
||||
/*
|
||||
* enable output
|
||||
*/
|
||||
i2c_dir_out();
|
||||
/*
|
||||
* remove ACK clock pulse
|
||||
*/
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
i2c_delay(CLOCK_LOW_TIME/2);
|
||||
return ack;
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: I2C::sendAck
|
||||
*#
|
||||
*# DESCRIPTION : Send ACK on received data
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
void
|
||||
i2c_sendack(void)
|
||||
{
|
||||
/*
|
||||
* enable output
|
||||
*/
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
i2c_dir_out();
|
||||
/*
|
||||
* set ack pulse high
|
||||
*/
|
||||
i2c_data(I2C_DATA_LOW);
|
||||
/*
|
||||
* generate clock pulse
|
||||
*/
|
||||
i2c_delay(CLOCK_HIGH_TIME/6);
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME);
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME/6);
|
||||
/*
|
||||
* reset data out
|
||||
*/
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
|
||||
i2c_dir_in();
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: i2c_sendnack
|
||||
*#
|
||||
*# DESCRIPTION : Sends NACK on received data
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
void
|
||||
i2c_sendnack(void)
|
||||
{
|
||||
/*
|
||||
* enable output
|
||||
*/
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
i2c_dir_out();
|
||||
/*
|
||||
* set data high
|
||||
*/
|
||||
i2c_data(I2C_DATA_HIGH);
|
||||
/*
|
||||
* generate clock pulse
|
||||
*/
|
||||
i2c_delay(CLOCK_HIGH_TIME/6);
|
||||
i2c_clk(I2C_CLOCK_HIGH);
|
||||
i2c_delay(CLOCK_HIGH_TIME);
|
||||
i2c_clk(I2C_CLOCK_LOW);
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
|
||||
i2c_dir_in();
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: i2c_write
|
||||
*#
|
||||
*# DESCRIPTION : Writes a value to an I2C device
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
int
|
||||
i2c_write(unsigned char theSlave, void *data, size_t nbytes)
|
||||
{
|
||||
int error, cntr = 3;
|
||||
unsigned char bytes_wrote = 0;
|
||||
unsigned char value;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i2c_lock, flags);
|
||||
|
||||
do {
|
||||
error = 0;
|
||||
|
||||
i2c_start();
|
||||
/*
|
||||
* send slave address
|
||||
*/
|
||||
i2c_outbyte((theSlave & 0xfe));
|
||||
/*
|
||||
* wait for ack
|
||||
*/
|
||||
if (!i2c_getack())
|
||||
error = 1;
|
||||
/*
|
||||
* send data
|
||||
*/
|
||||
for (bytes_wrote = 0; bytes_wrote < nbytes; bytes_wrote++) {
|
||||
memcpy(&value, data + bytes_wrote, sizeof value);
|
||||
i2c_outbyte(value);
|
||||
/*
|
||||
* now it's time to wait for ack
|
||||
*/
|
||||
if (!i2c_getack())
|
||||
error |= 4;
|
||||
}
|
||||
/*
|
||||
* end byte stream
|
||||
*/
|
||||
i2c_stop();
|
||||
|
||||
} while (error && cntr--);
|
||||
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
|
||||
spin_unlock_irqrestore(&i2c_lock, flags);
|
||||
|
||||
return -error;
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: i2c_read
|
||||
*#
|
||||
*# DESCRIPTION : Reads a value from an I2C device
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
int
|
||||
i2c_read(unsigned char theSlave, void *data, size_t nbytes)
|
||||
{
|
||||
unsigned char b = 0;
|
||||
unsigned char bytes_read = 0;
|
||||
int error, cntr = 3;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i2c_lock, flags);
|
||||
|
||||
do {
|
||||
error = 0;
|
||||
memset(data, 0, nbytes);
|
||||
/*
|
||||
* generate start condition
|
||||
*/
|
||||
i2c_start();
|
||||
/*
|
||||
* send slave address
|
||||
*/
|
||||
i2c_outbyte((theSlave | 0x01));
|
||||
/*
|
||||
* wait for ack
|
||||
*/
|
||||
if (!i2c_getack())
|
||||
error = 1;
|
||||
/*
|
||||
* fetch data
|
||||
*/
|
||||
for (bytes_read = 0; bytes_read < nbytes; bytes_read++) {
|
||||
b = i2c_inbyte();
|
||||
memcpy(data + bytes_read, &b, sizeof b);
|
||||
|
||||
if (bytes_read < (nbytes - 1))
|
||||
i2c_sendack();
|
||||
}
|
||||
/*
|
||||
* last received byte needs to be nacked
|
||||
* instead of acked
|
||||
*/
|
||||
i2c_sendnack();
|
||||
/*
|
||||
* end sequence
|
||||
*/
|
||||
i2c_stop();
|
||||
} while (error && cntr--);
|
||||
|
||||
spin_unlock_irqrestore(&i2c_lock, flags);
|
||||
|
||||
return -error;
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: i2c_writereg
|
||||
*#
|
||||
*# DESCRIPTION : Writes a value to an I2C device
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
int
|
||||
i2c_writereg(unsigned char theSlave, unsigned char theReg,
|
||||
unsigned char theValue)
|
||||
{
|
||||
int error, cntr = 3;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i2c_lock, flags);
|
||||
|
||||
do {
|
||||
error = 0;
|
||||
|
||||
i2c_start();
|
||||
/*
|
||||
* send slave address
|
||||
*/
|
||||
i2c_outbyte((theSlave & 0xfe));
|
||||
/*
|
||||
* wait for ack
|
||||
*/
|
||||
if(!i2c_getack())
|
||||
error = 1;
|
||||
/*
|
||||
* now select register
|
||||
*/
|
||||
i2c_dir_out();
|
||||
i2c_outbyte(theReg);
|
||||
/*
|
||||
* now it's time to wait for ack
|
||||
*/
|
||||
if(!i2c_getack())
|
||||
error |= 2;
|
||||
/*
|
||||
* send register register data
|
||||
*/
|
||||
i2c_outbyte(theValue);
|
||||
/*
|
||||
* now it's time to wait for ack
|
||||
*/
|
||||
if(!i2c_getack())
|
||||
error |= 4;
|
||||
/*
|
||||
* end byte stream
|
||||
*/
|
||||
i2c_stop();
|
||||
} while(error && cntr--);
|
||||
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
|
||||
spin_unlock_irqrestore(&i2c_lock, flags);
|
||||
|
||||
return -error;
|
||||
}
|
||||
|
||||
/*#---------------------------------------------------------------------------
|
||||
*#
|
||||
*# FUNCTION NAME: i2c_readreg
|
||||
*#
|
||||
*# DESCRIPTION : Reads a value from the decoder registers.
|
||||
*#
|
||||
*#--------------------------------------------------------------------------*/
|
||||
unsigned char
|
||||
i2c_readreg(unsigned char theSlave, unsigned char theReg)
|
||||
{
|
||||
unsigned char b = 0;
|
||||
int error, cntr = 3;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i2c_lock, flags);
|
||||
|
||||
do {
|
||||
error = 0;
|
||||
/*
|
||||
* generate start condition
|
||||
*/
|
||||
i2c_start();
|
||||
|
||||
/*
|
||||
* send slave address
|
||||
*/
|
||||
i2c_outbyte((theSlave & 0xfe));
|
||||
/*
|
||||
* wait for ack
|
||||
*/
|
||||
if(!i2c_getack())
|
||||
error = 1;
|
||||
/*
|
||||
* now select register
|
||||
*/
|
||||
i2c_dir_out();
|
||||
i2c_outbyte(theReg);
|
||||
/*
|
||||
* now it's time to wait for ack
|
||||
*/
|
||||
if(!i2c_getack())
|
||||
error |= 2;
|
||||
/*
|
||||
* repeat start condition
|
||||
*/
|
||||
i2c_delay(CLOCK_LOW_TIME);
|
||||
i2c_start();
|
||||
/*
|
||||
* send slave address
|
||||
*/
|
||||
i2c_outbyte(theSlave | 0x01);
|
||||
/*
|
||||
* wait for ack
|
||||
*/
|
||||
if(!i2c_getack())
|
||||
error |= 4;
|
||||
/*
|
||||
* fetch register
|
||||
*/
|
||||
b = i2c_inbyte();
|
||||
/*
|
||||
* last received byte needs to be nacked
|
||||
* instead of acked
|
||||
*/
|
||||
i2c_sendnack();
|
||||
/*
|
||||
* end sequence
|
||||
*/
|
||||
i2c_stop();
|
||||
|
||||
} while(error && cntr--);
|
||||
|
||||
spin_unlock_irqrestore(&i2c_lock, flags);
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
static int
|
||||
i2c_open(struct inode *inode, struct file *filp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
i2c_release(struct inode *inode, struct file *filp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Main device API. ioctl's to write or read to/from i2c registers.
|
||||
*/
|
||||
|
||||
static long
|
||||
i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int ret;
|
||||
if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case I2C_WRITEREG:
|
||||
/* write to an i2c slave */
|
||||
D(printk("i2cw %d %d %d\n",
|
||||
I2C_ARGSLAVE(arg),
|
||||
I2C_ARGREG(arg),
|
||||
I2C_ARGVALUE(arg)));
|
||||
|
||||
mutex_lock(&i2c_mutex);
|
||||
ret = i2c_writereg(I2C_ARGSLAVE(arg),
|
||||
I2C_ARGREG(arg),
|
||||
I2C_ARGVALUE(arg));
|
||||
mutex_unlock(&i2c_mutex);
|
||||
return ret;
|
||||
|
||||
case I2C_READREG:
|
||||
{
|
||||
unsigned char val;
|
||||
/* read from an i2c slave */
|
||||
D(printk("i2cr %d %d ",
|
||||
I2C_ARGSLAVE(arg),
|
||||
I2C_ARGREG(arg)));
|
||||
mutex_lock(&i2c_mutex);
|
||||
val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
|
||||
mutex_unlock(&i2c_mutex);
|
||||
D(printk("= %d\n", val));
|
||||
return val;
|
||||
}
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct file_operations i2c_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = i2c_ioctl,
|
||||
.open = i2c_open,
|
||||
.release = i2c_release,
|
||||
.llseek = noop_llseek,
|
||||
};
|
||||
|
||||
static int __init i2c_init(void)
|
||||
{
|
||||
static int res;
|
||||
static int first = 1;
|
||||
|
||||
if (!first)
|
||||
return res;
|
||||
|
||||
first = 0;
|
||||
|
||||
/* Setup and enable the DATA and CLK pins */
|
||||
|
||||
res = crisv32_io_get_name(&cris_i2c_data,
|
||||
CONFIG_ETRAX_V32_I2C_DATA_PORT);
|
||||
if (res < 0)
|
||||
return res;
|
||||
|
||||
res = crisv32_io_get_name(&cris_i2c_clk, CONFIG_ETRAX_V32_I2C_CLK_PORT);
|
||||
crisv32_io_set_dir(&cris_i2c_clk, crisv32_io_dir_out);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
static int __init i2c_register(void)
|
||||
{
|
||||
int res;
|
||||
|
||||
res = i2c_init();
|
||||
if (res < 0)
|
||||
return res;
|
||||
|
||||
/* register char device */
|
||||
|
||||
res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
|
||||
if (res < 0) {
|
||||
printk(KERN_ERR "i2c: couldn't get a major number.\n");
|
||||
return res;
|
||||
}
|
||||
|
||||
printk(KERN_INFO
|
||||
"I2C driver v2.2, (c) 1999-2007 Axis Communications AB\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
/* this makes sure that i2c_init is called during boot */
|
||||
module_init(i2c_register);
|
||||
|
||||
/****************** END OF FILE i2c.c ********************************/
|
|
@ -1,16 +0,0 @@
|
|||
|
||||
#include <linux/init.h>
|
||||
|
||||
/* High level I2C actions */
|
||||
int i2c_write(unsigned char theSlave, void *data, size_t nbytes);
|
||||
int i2c_read(unsigned char theSlave, void *data, size_t nbytes);
|
||||
int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
|
||||
unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
|
||||
|
||||
/* Low level I2C */
|
||||
void i2c_start(void);
|
||||
void i2c_stop(void);
|
||||
void i2c_outbyte(unsigned char x);
|
||||
unsigned char i2c_inbyte(void);
|
||||
int i2c_getack(void);
|
||||
void i2c_sendack(void);
|
|
@ -3,4 +3,3 @@
|
|||
#
|
||||
|
||||
obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
|
||||
obj-$(CONFIG_ETRAX_GPIO) += gpio.o
|
||||
|
|
|
@ -1,999 +0,0 @@
|
|||
/*
|
||||
* Artec-3 general port I/O device
|
||||
*
|
||||
* Copyright (c) 2007 Axis Communications AB
|
||||
*
|
||||
* Authors: Bjorn Wesen (initial version)
|
||||
* Ola Knutsson (LED handling)
|
||||
* Johan Adolfsson (read/set directions, write, port G,
|
||||
* port to ETRAX FS.
|
||||
* Ricard Wanderlof (PWM for Artpec-3)
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/poll.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#include <asm/etraxgpio.h>
|
||||
#include <hwregs/reg_map.h>
|
||||
#include <hwregs/reg_rdwr.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
#include <hwregs/intr_vect_defs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <mach/pinmux.h>
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
#include "../i2c.h"
|
||||
|
||||
#define VIRT_I2C_ADDR 0x40
|
||||
#endif
|
||||
|
||||
/* The following gio ports on ARTPEC-3 is available:
|
||||
* pa 32 bits
|
||||
* pb 32 bits
|
||||
* pc 16 bits
|
||||
* each port has a rw_px_dout, r_px_din and rw_px_oe register.
|
||||
*/
|
||||
|
||||
#define GPIO_MAJOR 120 /* experimental MAJOR number */
|
||||
|
||||
#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
|
||||
|
||||
#define D(x)
|
||||
|
||||
#if 0
|
||||
static int dp_cnt;
|
||||
#define DP(x) \
|
||||
do { \
|
||||
dp_cnt++; \
|
||||
if (dp_cnt % 1000 == 0) \
|
||||
x; \
|
||||
} while (0)
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
static DEFINE_MUTEX(gpio_mutex);
|
||||
static char gpio_name[] = "etrax gpio";
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
|
||||
unsigned long arg);
|
||||
#endif
|
||||
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
|
||||
static ssize_t gpio_write(struct file *file, const char __user *buf,
|
||||
size_t count, loff_t *off);
|
||||
static int gpio_open(struct inode *inode, struct file *filp);
|
||||
static int gpio_release(struct inode *inode, struct file *filp);
|
||||
static unsigned int gpio_poll(struct file *filp,
|
||||
struct poll_table_struct *wait);
|
||||
|
||||
/* private data per open() of this driver */
|
||||
|
||||
struct gpio_private {
|
||||
struct gpio_private *next;
|
||||
/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
|
||||
unsigned char clk_mask;
|
||||
unsigned char data_mask;
|
||||
unsigned char write_msb;
|
||||
unsigned char pad1;
|
||||
/* These fields are generic */
|
||||
unsigned long highalarm, lowalarm;
|
||||
wait_queue_head_t alarm_wq;
|
||||
int minor;
|
||||
};
|
||||
|
||||
static void gpio_set_alarm(struct gpio_private *priv);
|
||||
static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
|
||||
static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
|
||||
unsigned long arg);
|
||||
|
||||
|
||||
/* linked list of alarms to check for */
|
||||
|
||||
static struct gpio_private *alarmlist;
|
||||
|
||||
static int wanted_interrupts;
|
||||
|
||||
static DEFINE_SPINLOCK(gpio_lock);
|
||||
|
||||
#define NUM_PORTS (GPIO_MINOR_LAST+1)
|
||||
#define GIO_REG_RD_ADDR(reg) \
|
||||
(unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
|
||||
#define GIO_REG_WR_ADDR(reg) \
|
||||
(unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
|
||||
static unsigned long led_dummy;
|
||||
static unsigned long port_d_dummy; /* Only input on Artpec-3 */
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static unsigned long port_e_dummy; /* Non existent on Artpec-3 */
|
||||
static unsigned long virtual_dummy;
|
||||
static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
|
||||
static unsigned short cached_virtual_gpio_read;
|
||||
#endif
|
||||
|
||||
static unsigned long *data_out[NUM_PORTS] = {
|
||||
GIO_REG_WR_ADDR(rw_pa_dout),
|
||||
GIO_REG_WR_ADDR(rw_pb_dout),
|
||||
&led_dummy,
|
||||
GIO_REG_WR_ADDR(rw_pc_dout),
|
||||
&port_d_dummy,
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
&port_e_dummy,
|
||||
&virtual_dummy,
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned long *data_in[NUM_PORTS] = {
|
||||
GIO_REG_RD_ADDR(r_pa_din),
|
||||
GIO_REG_RD_ADDR(r_pb_din),
|
||||
&led_dummy,
|
||||
GIO_REG_RD_ADDR(r_pc_din),
|
||||
GIO_REG_RD_ADDR(r_pd_din),
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
&port_e_dummy,
|
||||
&virtual_dummy,
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned long changeable_dir[NUM_PORTS] = {
|
||||
CONFIG_ETRAX_PA_CHANGEABLE_DIR,
|
||||
CONFIG_ETRAX_PB_CHANGEABLE_DIR,
|
||||
0,
|
||||
CONFIG_ETRAX_PC_CHANGEABLE_DIR,
|
||||
0,
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
0,
|
||||
CONFIG_ETRAX_PV_CHANGEABLE_DIR,
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned long changeable_bits[NUM_PORTS] = {
|
||||
CONFIG_ETRAX_PA_CHANGEABLE_BITS,
|
||||
CONFIG_ETRAX_PB_CHANGEABLE_BITS,
|
||||
0,
|
||||
CONFIG_ETRAX_PC_CHANGEABLE_BITS,
|
||||
0,
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
0,
|
||||
CONFIG_ETRAX_PV_CHANGEABLE_BITS,
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned long *dir_oe[NUM_PORTS] = {
|
||||
GIO_REG_WR_ADDR(rw_pa_oe),
|
||||
GIO_REG_WR_ADDR(rw_pb_oe),
|
||||
&led_dummy,
|
||||
GIO_REG_WR_ADDR(rw_pc_oe),
|
||||
&port_d_dummy,
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
&port_e_dummy,
|
||||
&virtual_rw_pv_oe,
|
||||
#endif
|
||||
};
|
||||
|
||||
static void gpio_set_alarm(struct gpio_private *priv)
|
||||
{
|
||||
int bit;
|
||||
int intr_cfg;
|
||||
int mask;
|
||||
int pins;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
|
||||
pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
|
||||
mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
|
||||
|
||||
for (bit = 0; bit < 32; bit++) {
|
||||
int intr = bit % 8;
|
||||
int pin = bit / 8;
|
||||
if (priv->minor < GPIO_MINOR_LEDS)
|
||||
pin += priv->minor * 4;
|
||||
else
|
||||
pin += (priv->minor - 1) * 4;
|
||||
|
||||
if (priv->highalarm & (1<<bit)) {
|
||||
intr_cfg |= (regk_gio_hi << (intr * 3));
|
||||
mask |= 1 << intr;
|
||||
wanted_interrupts = mask & 0xff;
|
||||
pins |= pin << (intr * 4);
|
||||
} else if (priv->lowalarm & (1<<bit)) {
|
||||
intr_cfg |= (regk_gio_lo << (intr * 3));
|
||||
mask |= 1 << intr;
|
||||
wanted_interrupts = mask & 0xff;
|
||||
pins |= pin << (intr * 4);
|
||||
}
|
||||
}
|
||||
|
||||
REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
|
||||
REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
|
||||
REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
}
|
||||
|
||||
static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
|
||||
{
|
||||
unsigned int mask = 0;
|
||||
struct gpio_private *priv = file->private_data;
|
||||
unsigned long data;
|
||||
unsigned long tmp;
|
||||
|
||||
if (priv->minor >= GPIO_MINOR_PWM0 &&
|
||||
priv->minor <= GPIO_MINOR_LAST_PWM)
|
||||
return 0;
|
||||
|
||||
poll_wait(file, &priv->alarm_wq, wait);
|
||||
if (priv->minor <= GPIO_MINOR_D) {
|
||||
data = readl(data_in[priv->minor]);
|
||||
REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
|
||||
tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
|
||||
tmp &= I2C_INTERRUPT_BITS;
|
||||
tmp |= wanted_interrupts;
|
||||
REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
|
||||
} else
|
||||
return 0;
|
||||
|
||||
if ((data & priv->highalarm) || (~data & priv->lowalarm))
|
||||
mask = POLLIN|POLLRDNORM;
|
||||
|
||||
DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
|
||||
return mask;
|
||||
}
|
||||
|
||||
static irqreturn_t gpio_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
reg_gio_rw_intr_mask intr_mask;
|
||||
reg_gio_r_masked_intr masked_intr;
|
||||
reg_gio_rw_ack_intr ack_intr;
|
||||
unsigned long flags;
|
||||
unsigned long tmp;
|
||||
unsigned long tmp2;
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
unsigned char enable_gpiov_ack = 0;
|
||||
#endif
|
||||
|
||||
/* Find what PA interrupts are active */
|
||||
masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
|
||||
tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
|
||||
|
||||
/* Find those that we have enabled */
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
tmp &= wanted_interrupts;
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
/* Something changed on virtual GPIO. Interrupt is acked by
|
||||
* reading the device.
|
||||
*/
|
||||
if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
|
||||
sizeof(cached_virtual_gpio_read));
|
||||
enable_gpiov_ack = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Ack them */
|
||||
ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
|
||||
REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
|
||||
|
||||
/* Disable those interrupts.. */
|
||||
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
|
||||
tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
|
||||
tmp2 &= ~tmp;
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
/* Do not disable interrupt on virtual GPIO. Changes on virtual
|
||||
* pins are only noticed by an interrupt.
|
||||
*/
|
||||
if (enable_gpiov_ack)
|
||||
tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
#endif
|
||||
intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
|
||||
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
|
||||
|
||||
return IRQ_RETVAL(tmp);
|
||||
}
|
||||
|
||||
static void gpio_write_bit(unsigned long *port, unsigned char data, int bit,
|
||||
unsigned char clk_mask, unsigned char data_mask)
|
||||
{
|
||||
unsigned long shadow = readl(port) & ~clk_mask;
|
||||
writel(shadow, port);
|
||||
if (data & 1 << bit)
|
||||
shadow |= data_mask;
|
||||
else
|
||||
shadow &= ~data_mask;
|
||||
writel(shadow, port);
|
||||
/* For FPGA: min 5.0ns (DCC) before CCLK high */
|
||||
shadow |= clk_mask;
|
||||
writel(shadow, port);
|
||||
}
|
||||
|
||||
static void gpio_write_byte(struct gpio_private *priv, unsigned long *port,
|
||||
unsigned char data)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (priv->write_msb)
|
||||
for (i = 7; i >= 0; i--)
|
||||
gpio_write_bit(port, data, i, priv->clk_mask,
|
||||
priv->data_mask);
|
||||
else
|
||||
for (i = 0; i <= 7; i++)
|
||||
gpio_write_bit(port, data, i, priv->clk_mask,
|
||||
priv->data_mask);
|
||||
}
|
||||
|
||||
|
||||
static ssize_t gpio_write(struct file *file, const char __user *buf,
|
||||
size_t count, loff_t *off)
|
||||
{
|
||||
struct gpio_private *priv = file->private_data;
|
||||
unsigned long flags;
|
||||
ssize_t retval = count;
|
||||
/* Only bits 0-7 may be used for write operations but allow all
|
||||
devices except leds... */
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
if (priv->minor == GPIO_MINOR_V)
|
||||
return -EFAULT;
|
||||
#endif
|
||||
if (priv->minor == GPIO_MINOR_LEDS)
|
||||
return -EFAULT;
|
||||
|
||||
if (priv->minor >= GPIO_MINOR_PWM0 &&
|
||||
priv->minor <= GPIO_MINOR_LAST_PWM)
|
||||
return -EFAULT;
|
||||
|
||||
if (!access_ok(VERIFY_READ, buf, count))
|
||||
return -EFAULT;
|
||||
|
||||
/* It must have been configured using the IO_CFG_WRITE_MODE */
|
||||
/* Perhaps a better error code? */
|
||||
if (priv->clk_mask == 0 || priv->data_mask == 0)
|
||||
return -EPERM;
|
||||
|
||||
D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
|
||||
"msb: %i\n",
|
||||
count, priv->data_mask, priv->clk_mask, priv->write_msb));
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
while (count--)
|
||||
gpio_write_byte(priv, data_out[priv->minor], *buf++);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int gpio_open(struct inode *inode, struct file *filp)
|
||||
{
|
||||
struct gpio_private *priv;
|
||||
int p = iminor(inode);
|
||||
|
||||
if (p > GPIO_MINOR_LAST_PWM ||
|
||||
(p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
|
||||
return -EINVAL;
|
||||
|
||||
priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
|
||||
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_lock(&gpio_mutex);
|
||||
memset(priv, 0, sizeof(*priv));
|
||||
|
||||
priv->minor = p;
|
||||
filp->private_data = priv;
|
||||
|
||||
/* initialize the io/alarm struct, not for PWM ports though */
|
||||
if (p <= GPIO_MINOR_LAST) {
|
||||
|
||||
priv->clk_mask = 0;
|
||||
priv->data_mask = 0;
|
||||
priv->highalarm = 0;
|
||||
priv->lowalarm = 0;
|
||||
|
||||
init_waitqueue_head(&priv->alarm_wq);
|
||||
|
||||
/* link it into our alarmlist */
|
||||
spin_lock_irq(&gpio_lock);
|
||||
priv->next = alarmlist;
|
||||
alarmlist = priv;
|
||||
spin_unlock_irq(&gpio_lock);
|
||||
}
|
||||
|
||||
mutex_unlock(&gpio_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_release(struct inode *inode, struct file *filp)
|
||||
{
|
||||
struct gpio_private *p;
|
||||
struct gpio_private *todel;
|
||||
/* local copies while updating them: */
|
||||
unsigned long a_high, a_low;
|
||||
|
||||
/* prepare to free private structure */
|
||||
todel = filp->private_data;
|
||||
|
||||
/* unlink from alarmlist - only for non-PWM ports though */
|
||||
if (todel->minor <= GPIO_MINOR_LAST) {
|
||||
spin_lock_irq(&gpio_lock);
|
||||
p = alarmlist;
|
||||
|
||||
if (p == todel)
|
||||
alarmlist = todel->next;
|
||||
else {
|
||||
while (p->next != todel)
|
||||
p = p->next;
|
||||
p->next = todel->next;
|
||||
}
|
||||
|
||||
/* Check if there are still any alarms set */
|
||||
p = alarmlist;
|
||||
a_high = 0;
|
||||
a_low = 0;
|
||||
while (p) {
|
||||
if (p->minor == GPIO_MINOR_A) {
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
#endif
|
||||
a_high |= p->highalarm;
|
||||
a_low |= p->lowalarm;
|
||||
}
|
||||
|
||||
p = p->next;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
/* Variable 'a_low' needs to be set here again
|
||||
* to ensure that interrupt for virtual GPIO is handled.
|
||||
*/
|
||||
a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
#endif
|
||||
|
||||
spin_unlock_irq(&gpio_lock);
|
||||
}
|
||||
kfree(todel);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Main device API. ioctl's to read/set/clear bits, as well as to
|
||||
* set alarms to wait for using a subsequent select().
|
||||
*/
|
||||
|
||||
inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
|
||||
{
|
||||
/* Set direction 0=unchanged 1=input,
|
||||
* return mask with 1=input
|
||||
*/
|
||||
unsigned long flags;
|
||||
unsigned long dir_shadow;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
dir_shadow = readl(dir_oe[priv->minor]) &
|
||||
~(arg & changeable_dir[priv->minor]);
|
||||
writel(dir_shadow, dir_oe[priv->minor]);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
if (priv->minor == GPIO_MINOR_C)
|
||||
dir_shadow ^= 0xFFFF; /* Only 16 bits */
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
else if (priv->minor == GPIO_MINOR_V)
|
||||
dir_shadow ^= 0xFFFF; /* Only 16 bits */
|
||||
#endif
|
||||
else
|
||||
dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
|
||||
|
||||
return dir_shadow;
|
||||
|
||||
} /* setget_input */
|
||||
|
||||
static inline unsigned long setget_output(struct gpio_private *priv,
|
||||
unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long dir_shadow;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
dir_shadow = readl(dir_oe[priv->minor]) |
|
||||
(arg & changeable_dir[priv->minor]);
|
||||
writel(dir_shadow, dir_oe[priv->minor]);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
return dir_shadow;
|
||||
} /* setget_output */
|
||||
|
||||
static long gpio_ioctl_unlocked(struct file *file,
|
||||
unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long val;
|
||||
unsigned long shadow;
|
||||
struct gpio_private *priv = file->private_data;
|
||||
|
||||
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
|
||||
return -ENOTTY;
|
||||
|
||||
/* Check for special ioctl handlers first */
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
if (priv->minor == GPIO_MINOR_V)
|
||||
return virtual_gpio_ioctl(file, cmd, arg);
|
||||
#endif
|
||||
|
||||
if (priv->minor == GPIO_MINOR_LEDS)
|
||||
return gpio_leds_ioctl(cmd, arg);
|
||||
|
||||
if (priv->minor >= GPIO_MINOR_PWM0 &&
|
||||
priv->minor <= GPIO_MINOR_LAST_PWM)
|
||||
return gpio_pwm_ioctl(priv, cmd, arg);
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
|
||||
/* Read the port. */
|
||||
return readl(data_in[priv->minor]);
|
||||
case IO_SETBITS:
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
/* Set changeable bits with a 1 in arg. */
|
||||
shadow = readl(data_out[priv->minor]) |
|
||||
(arg & changeable_bits[priv->minor]);
|
||||
writel(shadow, data_out[priv->minor]);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
break;
|
||||
case IO_CLRBITS:
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
/* Clear changeable bits with a 1 in arg. */
|
||||
shadow = readl(data_out[priv->minor]) &
|
||||
~(arg & changeable_bits[priv->minor]);
|
||||
writel(shadow, data_out[priv->minor]);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
break;
|
||||
case IO_HIGHALARM:
|
||||
/* Set alarm when bits with 1 in arg go high. */
|
||||
priv->highalarm |= arg;
|
||||
gpio_set_alarm(priv);
|
||||
break;
|
||||
case IO_LOWALARM:
|
||||
/* Set alarm when bits with 1 in arg go low. */
|
||||
priv->lowalarm |= arg;
|
||||
gpio_set_alarm(priv);
|
||||
break;
|
||||
case IO_CLRALARM:
|
||||
/* Clear alarm for bits with 1 in arg. */
|
||||
priv->highalarm &= ~arg;
|
||||
priv->lowalarm &= ~arg;
|
||||
gpio_set_alarm(priv);
|
||||
break;
|
||||
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
|
||||
/* Read direction 0=input 1=output */
|
||||
return readl(dir_oe[priv->minor]);
|
||||
|
||||
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
|
||||
/* Set direction 0=unchanged 1=input,
|
||||
* return mask with 1=input
|
||||
*/
|
||||
return setget_input(priv, arg);
|
||||
|
||||
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
|
||||
/* Set direction 0=unchanged 1=output,
|
||||
* return mask with 1=output
|
||||
*/
|
||||
return setget_output(priv, arg);
|
||||
|
||||
case IO_CFG_WRITE_MODE:
|
||||
{
|
||||
int res = -EPERM;
|
||||
unsigned long dir_shadow, clk_mask, data_mask, write_msb;
|
||||
|
||||
clk_mask = arg & 0xFF;
|
||||
data_mask = (arg >> 8) & 0xFF;
|
||||
write_msb = (arg >> 16) & 0x01;
|
||||
|
||||
/* Check if we're allowed to change the bits and
|
||||
* the direction is correct
|
||||
*/
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
dir_shadow = readl(dir_oe[priv->minor]);
|
||||
if ((clk_mask & changeable_bits[priv->minor]) &&
|
||||
(data_mask & changeable_bits[priv->minor]) &&
|
||||
(clk_mask & dir_shadow) &&
|
||||
(data_mask & dir_shadow)) {
|
||||
priv->clk_mask = clk_mask;
|
||||
priv->data_mask = data_mask;
|
||||
priv->write_msb = write_msb;
|
||||
res = 0;
|
||||
}
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
return res;
|
||||
}
|
||||
case IO_READ_INBITS:
|
||||
/* *arg is result of reading the input pins */
|
||||
val = readl(data_in[priv->minor]);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
case IO_READ_OUTBITS:
|
||||
/* *arg is result of reading the output shadow */
|
||||
val = *data_out[priv->minor];
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case IO_SETGET_INPUT:
|
||||
/* bits set in *arg is set to input,
|
||||
* *arg updated with current input pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_input(priv, val);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case IO_SETGET_OUTPUT:
|
||||
/* bits set in *arg is set to output,
|
||||
* *arg updated with current output pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_output(priv, val);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
} /* switch */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
long ret;
|
||||
|
||||
mutex_lock(&gpio_mutex);
|
||||
ret = gpio_ioctl_unlocked(file, cmd, arg);
|
||||
mutex_unlock(&gpio_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned short val;
|
||||
unsigned short shadow;
|
||||
struct gpio_private *priv = file->private_data;
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_SETBITS:
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
/* Set changeable bits with a 1 in arg. */
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
shadow |= ~readl(dir_oe[priv->minor]) |
|
||||
(arg & changeable_bits[priv->minor]);
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
break;
|
||||
case IO_CLRBITS:
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
/* Clear changeable bits with a 1 in arg. */
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
shadow |= ~readl(dir_oe[priv->minor]) &
|
||||
~(arg & changeable_bits[priv->minor]);
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
break;
|
||||
case IO_HIGHALARM:
|
||||
/* Set alarm when bits with 1 in arg go high. */
|
||||
priv->highalarm |= arg;
|
||||
break;
|
||||
case IO_LOWALARM:
|
||||
/* Set alarm when bits with 1 in arg go low. */
|
||||
priv->lowalarm |= arg;
|
||||
break;
|
||||
case IO_CLRALARM:
|
||||
/* Clear alarm for bits with 1 in arg. */
|
||||
priv->highalarm &= ~arg;
|
||||
priv->lowalarm &= ~arg;
|
||||
break;
|
||||
case IO_CFG_WRITE_MODE:
|
||||
{
|
||||
unsigned long dir_shadow;
|
||||
dir_shadow = readl(dir_oe[priv->minor]);
|
||||
|
||||
priv->clk_mask = arg & 0xFF;
|
||||
priv->data_mask = (arg >> 8) & 0xFF;
|
||||
priv->write_msb = (arg >> 16) & 0x01;
|
||||
/* Check if we're allowed to change the bits and
|
||||
* the direction is correct
|
||||
*/
|
||||
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
|
||||
(priv->data_mask & changeable_bits[priv->minor]) &&
|
||||
(priv->clk_mask & dir_shadow) &&
|
||||
(priv->data_mask & dir_shadow))) {
|
||||
priv->clk_mask = 0;
|
||||
priv->data_mask = 0;
|
||||
return -EPERM;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case IO_READ_INBITS:
|
||||
/* *arg is result of reading the input pins */
|
||||
val = cached_virtual_gpio_read & ~readl(dir_oe[priv->minor]);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
|
||||
case IO_READ_OUTBITS:
|
||||
/* *arg is result of reading the output shadow */
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
|
||||
val &= readl(dir_oe[priv->minor]);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case IO_SETGET_INPUT:
|
||||
{
|
||||
/* bits set in *arg is set to input,
|
||||
* *arg updated with current input pins.
|
||||
*/
|
||||
unsigned short input_mask = ~readl(dir_oe[priv->minor]);
|
||||
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_input(priv, val);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
if ((input_mask & val) != input_mask) {
|
||||
/* Input pins changed. All ports desired as input
|
||||
* should be set to logic 1.
|
||||
*/
|
||||
unsigned short change = input_mask ^ val;
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
|
||||
sizeof(shadow));
|
||||
shadow &= ~change;
|
||||
shadow |= val;
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
|
||||
sizeof(shadow));
|
||||
}
|
||||
break;
|
||||
}
|
||||
case IO_SETGET_OUTPUT:
|
||||
/* bits set in *arg is set to output,
|
||||
* *arg updated with current output pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_output(priv, val);
|
||||
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
} /* switch */
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
|
||||
|
||||
static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned char green;
|
||||
unsigned char red;
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_LEDACTIVE_SET:
|
||||
green = ((unsigned char) arg) & 1;
|
||||
red = (((unsigned char) arg) >> 1) & 1;
|
||||
CRIS_LED_ACTIVE_SET_G(green);
|
||||
CRIS_LED_ACTIVE_SET_R(red);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
} /* switch */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
|
||||
{
|
||||
int pinmux_pwm = pinmux_pwm0 + pwm_port;
|
||||
int mode;
|
||||
reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
|
||||
.ccd_val = 0,
|
||||
.ccd_override = regk_gio_no,
|
||||
.mode = regk_gio_no
|
||||
};
|
||||
int allocstatus;
|
||||
|
||||
if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
|
||||
return -EFAULT;
|
||||
rw_pwm_ctrl.mode = mode;
|
||||
if (mode != PWM_OFF)
|
||||
allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
|
||||
else
|
||||
allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
|
||||
if (allocstatus)
|
||||
return allocstatus;
|
||||
REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
|
||||
12 * pwm_port, rw_pwm_ctrl);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
|
||||
{
|
||||
struct io_pwm_set_period periods;
|
||||
reg_gio_rw_pwm0_var rw_pwm_widths;
|
||||
|
||||
if (copy_from_user(&periods, (void __user *)arg, sizeof(periods)))
|
||||
return -EFAULT;
|
||||
if (periods.lo > 8191 || periods.hi > 8191)
|
||||
return -EINVAL;
|
||||
rw_pwm_widths.lo = periods.lo;
|
||||
rw_pwm_widths.hi = periods.hi;
|
||||
REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
|
||||
12 * pwm_port, rw_pwm_widths);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
|
||||
{
|
||||
unsigned int duty;
|
||||
reg_gio_rw_pwm0_data rw_pwm_duty;
|
||||
|
||||
if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
|
||||
return -EFAULT;
|
||||
if (duty > 255)
|
||||
return -EINVAL;
|
||||
rw_pwm_duty.data = duty;
|
||||
REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
|
||||
12 * pwm_port, rw_pwm_duty);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
int pwm_port = priv->minor - GPIO_MINOR_PWM0;
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_PWM_SET_MODE:
|
||||
return gpio_pwm_set_mode(arg, pwm_port);
|
||||
case IO_PWM_SET_PERIOD:
|
||||
return gpio_pwm_set_period(arg, pwm_port);
|
||||
case IO_PWM_SET_DUTY:
|
||||
return gpio_pwm_set_duty(arg, pwm_port);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct file_operations gpio_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.poll = gpio_poll,
|
||||
.unlocked_ioctl = gpio_ioctl,
|
||||
.write = gpio_write,
|
||||
.open = gpio_open,
|
||||
.release = gpio_release,
|
||||
.llseek = noop_llseek,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static void __init virtual_gpio_init(void)
|
||||
{
|
||||
reg_gio_rw_intr_cfg intr_cfg;
|
||||
reg_gio_rw_intr_mask intr_mask;
|
||||
unsigned short shadow;
|
||||
|
||||
shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
|
||||
shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
|
||||
/* Set interrupt mask and on what state the interrupt shall trigger.
|
||||
* For virtual gpio the interrupt shall trigger on logic '0'.
|
||||
*/
|
||||
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
|
||||
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
|
||||
|
||||
switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
|
||||
case 0:
|
||||
intr_cfg.pa0 = regk_gio_lo;
|
||||
intr_mask.pa0 = regk_gio_yes;
|
||||
break;
|
||||
case 1:
|
||||
intr_cfg.pa1 = regk_gio_lo;
|
||||
intr_mask.pa1 = regk_gio_yes;
|
||||
break;
|
||||
case 2:
|
||||
intr_cfg.pa2 = regk_gio_lo;
|
||||
intr_mask.pa2 = regk_gio_yes;
|
||||
break;
|
||||
case 3:
|
||||
intr_cfg.pa3 = regk_gio_lo;
|
||||
intr_mask.pa3 = regk_gio_yes;
|
||||
break;
|
||||
case 4:
|
||||
intr_cfg.pa4 = regk_gio_lo;
|
||||
intr_mask.pa4 = regk_gio_yes;
|
||||
break;
|
||||
case 5:
|
||||
intr_cfg.pa5 = regk_gio_lo;
|
||||
intr_mask.pa5 = regk_gio_yes;
|
||||
break;
|
||||
case 6:
|
||||
intr_cfg.pa6 = regk_gio_lo;
|
||||
intr_mask.pa6 = regk_gio_yes;
|
||||
break;
|
||||
case 7:
|
||||
intr_cfg.pa7 = regk_gio_lo;
|
||||
intr_mask.pa7 = regk_gio_yes;
|
||||
break;
|
||||
}
|
||||
|
||||
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
|
||||
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* main driver initialization routine, called from mem.c */
|
||||
|
||||
static int __init gpio_init(void)
|
||||
{
|
||||
int res, res2;
|
||||
|
||||
printk(KERN_INFO "ETRAX FS GPIO driver v2.7, (c) 2003-2008 "
|
||||
"Axis Communications AB\n");
|
||||
|
||||
/* do the formalities */
|
||||
|
||||
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
|
||||
if (res < 0) {
|
||||
printk(KERN_ERR "gpio: couldn't get a major number.\n");
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Clear all leds */
|
||||
CRIS_LED_NETWORK_GRP0_SET(0);
|
||||
CRIS_LED_NETWORK_GRP1_SET(0);
|
||||
CRIS_LED_ACTIVE_SET(0);
|
||||
CRIS_LED_DISK_READ(0);
|
||||
CRIS_LED_DISK_WRITE(0);
|
||||
|
||||
res2 = request_irq(GIO_INTR_VECT, gpio_interrupt,
|
||||
IRQF_SHARED, "gpio", &alarmlist);
|
||||
if (res2) {
|
||||
printk(KERN_ERR "err: irq for gpio\n");
|
||||
return res2;
|
||||
}
|
||||
|
||||
/* No IRQs by default. */
|
||||
REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
virtual_gpio_init();
|
||||
#endif
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/* this makes sure that gpio_init is called during kernel boot */
|
||||
|
||||
module_init(gpio_init);
|
|
@ -3,4 +3,3 @@
|
|||
#
|
||||
|
||||
obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
|
||||
obj-$(CONFIG_ETRAX_GPIO) += gpio.o
|
||||
|
|
|
@ -1,978 +0,0 @@
|
|||
/*
|
||||
* ETRAX CRISv32 general port I/O device
|
||||
*
|
||||
* Copyright (c) 1999-2006 Axis Communications AB
|
||||
*
|
||||
* Authors: Bjorn Wesen (initial version)
|
||||
* Ola Knutsson (LED handling)
|
||||
* Johan Adolfsson (read/set directions, write, port G,
|
||||
* port to ETRAX FS.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/poll.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#include <asm/etraxgpio.h>
|
||||
#include <hwregs/reg_map.h>
|
||||
#include <hwregs/reg_rdwr.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
#include <hwregs/intr_vect_defs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
#include "../i2c.h"
|
||||
|
||||
#define VIRT_I2C_ADDR 0x40
|
||||
#endif
|
||||
|
||||
/* The following gio ports on ETRAX FS is available:
|
||||
* pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
|
||||
* pb 18 bits
|
||||
* pc 18 bits
|
||||
* pd 18 bits
|
||||
* pe 18 bits
|
||||
* each port has a rw_px_dout, r_px_din and rw_px_oe register.
|
||||
*/
|
||||
|
||||
#define GPIO_MAJOR 120 /* experimental MAJOR number */
|
||||
|
||||
#define D(x)
|
||||
|
||||
#if 0
|
||||
static int dp_cnt;
|
||||
#define DP(x) \
|
||||
do { \
|
||||
dp_cnt++; \
|
||||
if (dp_cnt % 1000 == 0) \
|
||||
x; \
|
||||
} while (0)
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
static DEFINE_MUTEX(gpio_mutex);
|
||||
static char gpio_name[] = "etrax gpio";
|
||||
|
||||
#if 0
|
||||
static wait_queue_head_t *gpio_wq;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
|
||||
unsigned long arg);
|
||||
#endif
|
||||
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
|
||||
static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
|
||||
loff_t *off);
|
||||
static int gpio_open(struct inode *inode, struct file *filp);
|
||||
static int gpio_release(struct inode *inode, struct file *filp);
|
||||
static unsigned int gpio_poll(struct file *filp,
|
||||
struct poll_table_struct *wait);
|
||||
|
||||
/* private data per open() of this driver */
|
||||
|
||||
struct gpio_private {
|
||||
struct gpio_private *next;
|
||||
/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
|
||||
unsigned char clk_mask;
|
||||
unsigned char data_mask;
|
||||
unsigned char write_msb;
|
||||
unsigned char pad1;
|
||||
/* These fields are generic */
|
||||
unsigned long highalarm, lowalarm;
|
||||
wait_queue_head_t alarm_wq;
|
||||
int minor;
|
||||
};
|
||||
|
||||
/* linked list of alarms to check for */
|
||||
|
||||
static struct gpio_private *alarmlist;
|
||||
|
||||
static int gpio_some_alarms; /* Set if someone uses alarm */
|
||||
static unsigned long gpio_pa_high_alarms;
|
||||
static unsigned long gpio_pa_low_alarms;
|
||||
|
||||
static DEFINE_SPINLOCK(alarm_lock);
|
||||
|
||||
#define NUM_PORTS (GPIO_MINOR_LAST+1)
|
||||
#define GIO_REG_RD_ADDR(reg) \
|
||||
(volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
|
||||
#define GIO_REG_WR_ADDR(reg) \
|
||||
(volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
|
||||
unsigned long led_dummy;
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static unsigned long virtual_dummy;
|
||||
static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
|
||||
static unsigned short cached_virtual_gpio_read;
|
||||
#endif
|
||||
|
||||
static volatile unsigned long *data_out[NUM_PORTS] = {
|
||||
GIO_REG_WR_ADDR(rw_pa_dout),
|
||||
GIO_REG_WR_ADDR(rw_pb_dout),
|
||||
&led_dummy,
|
||||
GIO_REG_WR_ADDR(rw_pc_dout),
|
||||
GIO_REG_WR_ADDR(rw_pd_dout),
|
||||
GIO_REG_WR_ADDR(rw_pe_dout),
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
&virtual_dummy,
|
||||
#endif
|
||||
};
|
||||
|
||||
static volatile unsigned long *data_in[NUM_PORTS] = {
|
||||
GIO_REG_RD_ADDR(r_pa_din),
|
||||
GIO_REG_RD_ADDR(r_pb_din),
|
||||
&led_dummy,
|
||||
GIO_REG_RD_ADDR(r_pc_din),
|
||||
GIO_REG_RD_ADDR(r_pd_din),
|
||||
GIO_REG_RD_ADDR(r_pe_din),
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
&virtual_dummy,
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned long changeable_dir[NUM_PORTS] = {
|
||||
CONFIG_ETRAX_PA_CHANGEABLE_DIR,
|
||||
CONFIG_ETRAX_PB_CHANGEABLE_DIR,
|
||||
0,
|
||||
CONFIG_ETRAX_PC_CHANGEABLE_DIR,
|
||||
CONFIG_ETRAX_PD_CHANGEABLE_DIR,
|
||||
CONFIG_ETRAX_PE_CHANGEABLE_DIR,
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
CONFIG_ETRAX_PV_CHANGEABLE_DIR,
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned long changeable_bits[NUM_PORTS] = {
|
||||
CONFIG_ETRAX_PA_CHANGEABLE_BITS,
|
||||
CONFIG_ETRAX_PB_CHANGEABLE_BITS,
|
||||
0,
|
||||
CONFIG_ETRAX_PC_CHANGEABLE_BITS,
|
||||
CONFIG_ETRAX_PD_CHANGEABLE_BITS,
|
||||
CONFIG_ETRAX_PE_CHANGEABLE_BITS,
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
CONFIG_ETRAX_PV_CHANGEABLE_BITS,
|
||||
#endif
|
||||
};
|
||||
|
||||
static volatile unsigned long *dir_oe[NUM_PORTS] = {
|
||||
GIO_REG_WR_ADDR(rw_pa_oe),
|
||||
GIO_REG_WR_ADDR(rw_pb_oe),
|
||||
&led_dummy,
|
||||
GIO_REG_WR_ADDR(rw_pc_oe),
|
||||
GIO_REG_WR_ADDR(rw_pd_oe),
|
||||
GIO_REG_WR_ADDR(rw_pe_oe),
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
&virtual_rw_pv_oe,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
|
||||
{
|
||||
unsigned int mask = 0;
|
||||
struct gpio_private *priv = file->private_data;
|
||||
unsigned long data;
|
||||
poll_wait(file, &priv->alarm_wq, wait);
|
||||
if (priv->minor == GPIO_MINOR_A) {
|
||||
reg_gio_rw_intr_cfg intr_cfg;
|
||||
unsigned long tmp;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din,
|
||||
REG_RD(gio, regi_gio, r_pa_din));
|
||||
/* PA has support for interrupt
|
||||
* lets activate high for those low and with highalarm set
|
||||
*/
|
||||
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
|
||||
|
||||
tmp = ~data & priv->highalarm & 0xFF;
|
||||
if (tmp & (1 << 0))
|
||||
intr_cfg.pa0 = regk_gio_hi;
|
||||
if (tmp & (1 << 1))
|
||||
intr_cfg.pa1 = regk_gio_hi;
|
||||
if (tmp & (1 << 2))
|
||||
intr_cfg.pa2 = regk_gio_hi;
|
||||
if (tmp & (1 << 3))
|
||||
intr_cfg.pa3 = regk_gio_hi;
|
||||
if (tmp & (1 << 4))
|
||||
intr_cfg.pa4 = regk_gio_hi;
|
||||
if (tmp & (1 << 5))
|
||||
intr_cfg.pa5 = regk_gio_hi;
|
||||
if (tmp & (1 << 6))
|
||||
intr_cfg.pa6 = regk_gio_hi;
|
||||
if (tmp & (1 << 7))
|
||||
intr_cfg.pa7 = regk_gio_hi;
|
||||
/*
|
||||
* lets activate low for those high and with lowalarm set
|
||||
*/
|
||||
tmp = data & priv->lowalarm & 0xFF;
|
||||
if (tmp & (1 << 0))
|
||||
intr_cfg.pa0 = regk_gio_lo;
|
||||
if (tmp & (1 << 1))
|
||||
intr_cfg.pa1 = regk_gio_lo;
|
||||
if (tmp & (1 << 2))
|
||||
intr_cfg.pa2 = regk_gio_lo;
|
||||
if (tmp & (1 << 3))
|
||||
intr_cfg.pa3 = regk_gio_lo;
|
||||
if (tmp & (1 << 4))
|
||||
intr_cfg.pa4 = regk_gio_lo;
|
||||
if (tmp & (1 << 5))
|
||||
intr_cfg.pa5 = regk_gio_lo;
|
||||
if (tmp & (1 << 6))
|
||||
intr_cfg.pa6 = regk_gio_lo;
|
||||
if (tmp & (1 << 7))
|
||||
intr_cfg.pa7 = regk_gio_lo;
|
||||
|
||||
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
|
||||
local_irq_restore(flags);
|
||||
} else if (priv->minor <= GPIO_MINOR_E)
|
||||
data = *data_in[priv->minor];
|
||||
else
|
||||
return 0;
|
||||
|
||||
if ((data & priv->highalarm) || (~data & priv->lowalarm))
|
||||
mask = POLLIN|POLLRDNORM;
|
||||
|
||||
DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
|
||||
return mask;
|
||||
}
|
||||
|
||||
int etrax_gpio_wake_up_check(void)
|
||||
{
|
||||
struct gpio_private *priv;
|
||||
unsigned long data = 0;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
spin_lock_irqsave(&alarm_lock, flags);
|
||||
priv = alarmlist;
|
||||
while (priv) {
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
if (priv->minor == GPIO_MINOR_V)
|
||||
data = (unsigned long)cached_virtual_gpio_read;
|
||||
else {
|
||||
data = *data_in[priv->minor];
|
||||
if (priv->minor == GPIO_MINOR_A)
|
||||
priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
}
|
||||
#else
|
||||
data = *data_in[priv->minor];
|
||||
#endif
|
||||
if ((data & priv->highalarm) ||
|
||||
(~data & priv->lowalarm)) {
|
||||
DP(printk(KERN_DEBUG
|
||||
"etrax_gpio_wake_up_check %i\n", priv->minor));
|
||||
wake_up_interruptible(&priv->alarm_wq);
|
||||
ret = 1;
|
||||
}
|
||||
priv = priv->next;
|
||||
}
|
||||
spin_unlock_irqrestore(&alarm_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static irqreturn_t
|
||||
gpio_poll_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
if (gpio_some_alarms)
|
||||
return IRQ_RETVAL(etrax_gpio_wake_up_check());
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static irqreturn_t
|
||||
gpio_pa_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
reg_gio_rw_intr_mask intr_mask;
|
||||
reg_gio_r_masked_intr masked_intr;
|
||||
reg_gio_rw_ack_intr ack_intr;
|
||||
unsigned long tmp;
|
||||
unsigned long tmp2;
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
unsigned char enable_gpiov_ack = 0;
|
||||
#endif
|
||||
|
||||
/* Find what PA interrupts are active */
|
||||
masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
|
||||
tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
|
||||
|
||||
/* Find those that we have enabled */
|
||||
spin_lock(&alarm_lock);
|
||||
tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
|
||||
spin_unlock(&alarm_lock);
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
/* Something changed on virtual GPIO. Interrupt is acked by
|
||||
* reading the device.
|
||||
*/
|
||||
if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
|
||||
sizeof(cached_virtual_gpio_read));
|
||||
enable_gpiov_ack = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Ack them */
|
||||
ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
|
||||
REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
|
||||
|
||||
/* Disable those interrupts.. */
|
||||
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
|
||||
tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
|
||||
tmp2 &= ~tmp;
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
/* Do not disable interrupt on virtual GPIO. Changes on virtual
|
||||
* pins are only noticed by an interrupt.
|
||||
*/
|
||||
if (enable_gpiov_ack)
|
||||
tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
#endif
|
||||
intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
|
||||
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
|
||||
|
||||
if (gpio_some_alarms)
|
||||
return IRQ_RETVAL(etrax_gpio_wake_up_check());
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
|
||||
static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
|
||||
loff_t *off)
|
||||
{
|
||||
struct gpio_private *priv = file->private_data;
|
||||
unsigned char data, clk_mask, data_mask, write_msb;
|
||||
unsigned long flags;
|
||||
unsigned long shadow;
|
||||
volatile unsigned long *port;
|
||||
ssize_t retval = count;
|
||||
/* Only bits 0-7 may be used for write operations but allow all
|
||||
devices except leds... */
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
if (priv->minor == GPIO_MINOR_V)
|
||||
return -EFAULT;
|
||||
#endif
|
||||
if (priv->minor == GPIO_MINOR_LEDS)
|
||||
return -EFAULT;
|
||||
|
||||
if (!access_ok(VERIFY_READ, buf, count))
|
||||
return -EFAULT;
|
||||
clk_mask = priv->clk_mask;
|
||||
data_mask = priv->data_mask;
|
||||
/* It must have been configured using the IO_CFG_WRITE_MODE */
|
||||
/* Perhaps a better error code? */
|
||||
if (clk_mask == 0 || data_mask == 0)
|
||||
return -EPERM;
|
||||
write_msb = priv->write_msb;
|
||||
D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
|
||||
"msb: %i\n", count, data_mask, clk_mask, write_msb));
|
||||
port = data_out[priv->minor];
|
||||
|
||||
while (count--) {
|
||||
int i;
|
||||
data = *buf++;
|
||||
if (priv->write_msb) {
|
||||
for (i = 7; i >= 0; i--) {
|
||||
local_irq_save(flags);
|
||||
shadow = *port;
|
||||
*port = shadow &= ~clk_mask;
|
||||
if (data & 1<<i)
|
||||
*port = shadow |= data_mask;
|
||||
else
|
||||
*port = shadow &= ~data_mask;
|
||||
/* For FPGA: min 5.0ns (DCC) before CCLK high */
|
||||
*port = shadow |= clk_mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i <= 7; i++) {
|
||||
local_irq_save(flags);
|
||||
shadow = *port;
|
||||
*port = shadow &= ~clk_mask;
|
||||
if (data & 1<<i)
|
||||
*port = shadow |= data_mask;
|
||||
else
|
||||
*port = shadow &= ~data_mask;
|
||||
/* For FPGA: min 5.0ns (DCC) before CCLK high */
|
||||
*port = shadow |= clk_mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
}
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int
|
||||
gpio_open(struct inode *inode, struct file *filp)
|
||||
{
|
||||
struct gpio_private *priv;
|
||||
int p = iminor(inode);
|
||||
|
||||
if (p > GPIO_MINOR_LAST)
|
||||
return -EINVAL;
|
||||
|
||||
priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_lock(&gpio_mutex);
|
||||
|
||||
priv->minor = p;
|
||||
|
||||
/* initialize the io/alarm struct */
|
||||
|
||||
priv->clk_mask = 0;
|
||||
priv->data_mask = 0;
|
||||
priv->highalarm = 0;
|
||||
priv->lowalarm = 0;
|
||||
init_waitqueue_head(&priv->alarm_wq);
|
||||
|
||||
filp->private_data = (void *)priv;
|
||||
|
||||
/* link it into our alarmlist */
|
||||
spin_lock_irq(&alarm_lock);
|
||||
priv->next = alarmlist;
|
||||
alarmlist = priv;
|
||||
spin_unlock_irq(&alarm_lock);
|
||||
|
||||
mutex_unlock(&gpio_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gpio_release(struct inode *inode, struct file *filp)
|
||||
{
|
||||
struct gpio_private *p;
|
||||
struct gpio_private *todel;
|
||||
/* local copies while updating them: */
|
||||
unsigned long a_high, a_low;
|
||||
unsigned long some_alarms;
|
||||
|
||||
/* unlink from alarmlist and free the private structure */
|
||||
|
||||
spin_lock_irq(&alarm_lock);
|
||||
p = alarmlist;
|
||||
todel = filp->private_data;
|
||||
|
||||
if (p == todel) {
|
||||
alarmlist = todel->next;
|
||||
} else {
|
||||
while (p->next != todel)
|
||||
p = p->next;
|
||||
p->next = todel->next;
|
||||
}
|
||||
|
||||
kfree(todel);
|
||||
/* Check if there are still any alarms set */
|
||||
p = alarmlist;
|
||||
some_alarms = 0;
|
||||
a_high = 0;
|
||||
a_low = 0;
|
||||
while (p) {
|
||||
if (p->minor == GPIO_MINOR_A) {
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
#endif
|
||||
a_high |= p->highalarm;
|
||||
a_low |= p->lowalarm;
|
||||
}
|
||||
|
||||
if (p->highalarm | p->lowalarm)
|
||||
some_alarms = 1;
|
||||
p = p->next;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
/* Variables 'some_alarms' and 'a_low' needs to be set here again
|
||||
* to ensure that interrupt for virtual GPIO is handled.
|
||||
*/
|
||||
some_alarms = 1;
|
||||
a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
#endif
|
||||
|
||||
gpio_some_alarms = some_alarms;
|
||||
gpio_pa_high_alarms = a_high;
|
||||
gpio_pa_low_alarms = a_low;
|
||||
spin_unlock_irq(&alarm_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Main device API. ioctl's to read/set/clear bits, as well as to
|
||||
* set alarms to wait for using a subsequent select().
|
||||
*/
|
||||
|
||||
inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
|
||||
{
|
||||
/* Set direction 0=unchanged 1=input,
|
||||
* return mask with 1=input
|
||||
*/
|
||||
unsigned long flags;
|
||||
unsigned long dir_shadow;
|
||||
|
||||
local_irq_save(flags);
|
||||
dir_shadow = *dir_oe[priv->minor];
|
||||
dir_shadow &= ~(arg & changeable_dir[priv->minor]);
|
||||
*dir_oe[priv->minor] = dir_shadow;
|
||||
local_irq_restore(flags);
|
||||
|
||||
if (priv->minor == GPIO_MINOR_A)
|
||||
dir_shadow ^= 0xFF; /* Only 8 bits */
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
else if (priv->minor == GPIO_MINOR_V)
|
||||
dir_shadow ^= 0xFFFF; /* Only 16 bits */
|
||||
#endif
|
||||
else
|
||||
dir_shadow ^= 0x3FFFF; /* Only 18 bits */
|
||||
return dir_shadow;
|
||||
|
||||
} /* setget_input */
|
||||
|
||||
inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long dir_shadow;
|
||||
|
||||
local_irq_save(flags);
|
||||
dir_shadow = *dir_oe[priv->minor];
|
||||
dir_shadow |= (arg & changeable_dir[priv->minor]);
|
||||
*dir_oe[priv->minor] = dir_shadow;
|
||||
local_irq_restore(flags);
|
||||
return dir_shadow;
|
||||
} /* setget_output */
|
||||
|
||||
static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
|
||||
|
||||
static int
|
||||
gpio_ioctl_unlocked(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long val;
|
||||
unsigned long shadow;
|
||||
struct gpio_private *priv = file->private_data;
|
||||
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
|
||||
return -EINVAL;
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
if (priv->minor == GPIO_MINOR_V)
|
||||
return virtual_gpio_ioctl(file, cmd, arg);
|
||||
#endif
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
|
||||
/* Read the port. */
|
||||
return *data_in[priv->minor];
|
||||
break;
|
||||
case IO_SETBITS:
|
||||
local_irq_save(flags);
|
||||
/* Set changeable bits with a 1 in arg. */
|
||||
shadow = *data_out[priv->minor];
|
||||
shadow |= (arg & changeable_bits[priv->minor]);
|
||||
*data_out[priv->minor] = shadow;
|
||||
local_irq_restore(flags);
|
||||
break;
|
||||
case IO_CLRBITS:
|
||||
local_irq_save(flags);
|
||||
/* Clear changeable bits with a 1 in arg. */
|
||||
shadow = *data_out[priv->minor];
|
||||
shadow &= ~(arg & changeable_bits[priv->minor]);
|
||||
*data_out[priv->minor] = shadow;
|
||||
local_irq_restore(flags);
|
||||
break;
|
||||
case IO_HIGHALARM:
|
||||
/* Set alarm when bits with 1 in arg go high. */
|
||||
priv->highalarm |= arg;
|
||||
spin_lock_irqsave(&alarm_lock, flags);
|
||||
gpio_some_alarms = 1;
|
||||
if (priv->minor == GPIO_MINOR_A)
|
||||
gpio_pa_high_alarms |= arg;
|
||||
spin_unlock_irqrestore(&alarm_lock, flags);
|
||||
break;
|
||||
case IO_LOWALARM:
|
||||
/* Set alarm when bits with 1 in arg go low. */
|
||||
priv->lowalarm |= arg;
|
||||
spin_lock_irqsave(&alarm_lock, flags);
|
||||
gpio_some_alarms = 1;
|
||||
if (priv->minor == GPIO_MINOR_A)
|
||||
gpio_pa_low_alarms |= arg;
|
||||
spin_unlock_irqrestore(&alarm_lock, flags);
|
||||
break;
|
||||
case IO_CLRALARM:
|
||||
/* Clear alarm for bits with 1 in arg. */
|
||||
priv->highalarm &= ~arg;
|
||||
priv->lowalarm &= ~arg;
|
||||
spin_lock_irqsave(&alarm_lock, flags);
|
||||
if (priv->minor == GPIO_MINOR_A) {
|
||||
if (gpio_pa_high_alarms & arg ||
|
||||
gpio_pa_low_alarms & arg)
|
||||
/* Must update the gpio_pa_*alarms masks */
|
||||
;
|
||||
}
|
||||
spin_unlock_irqrestore(&alarm_lock, flags);
|
||||
break;
|
||||
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
|
||||
/* Read direction 0=input 1=output */
|
||||
return *dir_oe[priv->minor];
|
||||
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
|
||||
/* Set direction 0=unchanged 1=input,
|
||||
* return mask with 1=input
|
||||
*/
|
||||
return setget_input(priv, arg);
|
||||
break;
|
||||
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
|
||||
/* Set direction 0=unchanged 1=output,
|
||||
* return mask with 1=output
|
||||
*/
|
||||
return setget_output(priv, arg);
|
||||
|
||||
case IO_CFG_WRITE_MODE:
|
||||
{
|
||||
unsigned long dir_shadow;
|
||||
dir_shadow = *dir_oe[priv->minor];
|
||||
|
||||
priv->clk_mask = arg & 0xFF;
|
||||
priv->data_mask = (arg >> 8) & 0xFF;
|
||||
priv->write_msb = (arg >> 16) & 0x01;
|
||||
/* Check if we're allowed to change the bits and
|
||||
* the direction is correct
|
||||
*/
|
||||
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
|
||||
(priv->data_mask & changeable_bits[priv->minor]) &&
|
||||
(priv->clk_mask & dir_shadow) &&
|
||||
(priv->data_mask & dir_shadow))) {
|
||||
priv->clk_mask = 0;
|
||||
priv->data_mask = 0;
|
||||
return -EPERM;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case IO_READ_INBITS:
|
||||
/* *arg is result of reading the input pins */
|
||||
val = *data_in[priv->minor];
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
break;
|
||||
case IO_READ_OUTBITS:
|
||||
/* *arg is result of reading the output shadow */
|
||||
val = *data_out[priv->minor];
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case IO_SETGET_INPUT:
|
||||
/* bits set in *arg is set to input,
|
||||
* *arg updated with current input pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_input(priv, val);
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case IO_SETGET_OUTPUT:
|
||||
/* bits set in *arg is set to output,
|
||||
* *arg updated with current output pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_output(priv, val);
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
default:
|
||||
if (priv->minor == GPIO_MINOR_LEDS)
|
||||
return gpio_leds_ioctl(cmd, arg);
|
||||
else
|
||||
return -EINVAL;
|
||||
} /* switch */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
long ret;
|
||||
|
||||
mutex_lock(&gpio_mutex);
|
||||
ret = gpio_ioctl_unlocked(file, cmd, arg);
|
||||
mutex_unlock(&gpio_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static int
|
||||
virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned short val;
|
||||
unsigned short shadow;
|
||||
struct gpio_private *priv = file->private_data;
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_SETBITS:
|
||||
local_irq_save(flags);
|
||||
/* Set changeable bits with a 1 in arg. */
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
shadow |= ~*dir_oe[priv->minor];
|
||||
shadow |= (arg & changeable_bits[priv->minor]);
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
local_irq_restore(flags);
|
||||
break;
|
||||
case IO_CLRBITS:
|
||||
local_irq_save(flags);
|
||||
/* Clear changeable bits with a 1 in arg. */
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
shadow |= ~*dir_oe[priv->minor];
|
||||
shadow &= ~(arg & changeable_bits[priv->minor]);
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
local_irq_restore(flags);
|
||||
break;
|
||||
case IO_HIGHALARM:
|
||||
/* Set alarm when bits with 1 in arg go high. */
|
||||
priv->highalarm |= arg;
|
||||
spin_lock(&alarm_lock);
|
||||
gpio_some_alarms = 1;
|
||||
spin_unlock(&alarm_lock);
|
||||
break;
|
||||
case IO_LOWALARM:
|
||||
/* Set alarm when bits with 1 in arg go low. */
|
||||
priv->lowalarm |= arg;
|
||||
spin_lock(&alarm_lock);
|
||||
gpio_some_alarms = 1;
|
||||
spin_unlock(&alarm_lock);
|
||||
break;
|
||||
case IO_CLRALARM:
|
||||
/* Clear alarm for bits with 1 in arg. */
|
||||
priv->highalarm &= ~arg;
|
||||
priv->lowalarm &= ~arg;
|
||||
spin_lock(&alarm_lock);
|
||||
spin_unlock(&alarm_lock);
|
||||
break;
|
||||
case IO_CFG_WRITE_MODE:
|
||||
{
|
||||
unsigned long dir_shadow;
|
||||
dir_shadow = *dir_oe[priv->minor];
|
||||
|
||||
priv->clk_mask = arg & 0xFF;
|
||||
priv->data_mask = (arg >> 8) & 0xFF;
|
||||
priv->write_msb = (arg >> 16) & 0x01;
|
||||
/* Check if we're allowed to change the bits and
|
||||
* the direction is correct
|
||||
*/
|
||||
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
|
||||
(priv->data_mask & changeable_bits[priv->minor]) &&
|
||||
(priv->clk_mask & dir_shadow) &&
|
||||
(priv->data_mask & dir_shadow))) {
|
||||
priv->clk_mask = 0;
|
||||
priv->data_mask = 0;
|
||||
return -EPERM;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case IO_READ_INBITS:
|
||||
/* *arg is result of reading the input pins */
|
||||
val = cached_virtual_gpio_read;
|
||||
val &= ~*dir_oe[priv->minor];
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
break;
|
||||
case IO_READ_OUTBITS:
|
||||
/* *arg is result of reading the output shadow */
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
|
||||
val &= *dir_oe[priv->minor];
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case IO_SETGET_INPUT:
|
||||
{
|
||||
/* bits set in *arg is set to input,
|
||||
* *arg updated with current input pins.
|
||||
*/
|
||||
unsigned short input_mask = ~*dir_oe[priv->minor];
|
||||
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_input(priv, val);
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
if ((input_mask & val) != input_mask) {
|
||||
/* Input pins changed. All ports desired as input
|
||||
* should be set to logic 1.
|
||||
*/
|
||||
unsigned short change = input_mask ^ val;
|
||||
i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
|
||||
sizeof(shadow));
|
||||
shadow &= ~change;
|
||||
shadow |= val;
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
|
||||
sizeof(shadow));
|
||||
}
|
||||
break;
|
||||
}
|
||||
case IO_SETGET_OUTPUT:
|
||||
/* bits set in *arg is set to output,
|
||||
* *arg updated with current output pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
||||
return -EFAULT;
|
||||
val = setget_output(priv, val);
|
||||
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
} /* switch */
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
|
||||
|
||||
static int
|
||||
gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned char green;
|
||||
unsigned char red;
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_LEDACTIVE_SET:
|
||||
green = ((unsigned char) arg) & 1;
|
||||
red = (((unsigned char) arg) >> 1) & 1;
|
||||
CRIS_LED_ACTIVE_SET_G(green);
|
||||
CRIS_LED_ACTIVE_SET_R(red);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
} /* switch */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct file_operations gpio_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.poll = gpio_poll,
|
||||
.unlocked_ioctl = gpio_ioctl,
|
||||
.write = gpio_write,
|
||||
.open = gpio_open,
|
||||
.release = gpio_release,
|
||||
.llseek = noop_llseek,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
static void
|
||||
virtual_gpio_init(void)
|
||||
{
|
||||
reg_gio_rw_intr_cfg intr_cfg;
|
||||
reg_gio_rw_intr_mask intr_mask;
|
||||
unsigned short shadow;
|
||||
|
||||
shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
|
||||
shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
|
||||
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
||||
|
||||
/* Set interrupt mask and on what state the interrupt shall trigger.
|
||||
* For virtual gpio the interrupt shall trigger on logic '0'.
|
||||
*/
|
||||
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
|
||||
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
|
||||
|
||||
switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
|
||||
case 0:
|
||||
intr_cfg.pa0 = regk_gio_lo;
|
||||
intr_mask.pa0 = regk_gio_yes;
|
||||
break;
|
||||
case 1:
|
||||
intr_cfg.pa1 = regk_gio_lo;
|
||||
intr_mask.pa1 = regk_gio_yes;
|
||||
break;
|
||||
case 2:
|
||||
intr_cfg.pa2 = regk_gio_lo;
|
||||
intr_mask.pa2 = regk_gio_yes;
|
||||
break;
|
||||
case 3:
|
||||
intr_cfg.pa3 = regk_gio_lo;
|
||||
intr_mask.pa3 = regk_gio_yes;
|
||||
break;
|
||||
case 4:
|
||||
intr_cfg.pa4 = regk_gio_lo;
|
||||
intr_mask.pa4 = regk_gio_yes;
|
||||
break;
|
||||
case 5:
|
||||
intr_cfg.pa5 = regk_gio_lo;
|
||||
intr_mask.pa5 = regk_gio_yes;
|
||||
break;
|
||||
case 6:
|
||||
intr_cfg.pa6 = regk_gio_lo;
|
||||
intr_mask.pa6 = regk_gio_yes;
|
||||
break;
|
||||
case 7:
|
||||
intr_cfg.pa7 = regk_gio_lo;
|
||||
intr_mask.pa7 = regk_gio_yes;
|
||||
break;
|
||||
}
|
||||
|
||||
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
|
||||
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
|
||||
|
||||
gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
||||
gpio_some_alarms = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* main driver initialization routine, called from mem.c */
|
||||
|
||||
static __init int
|
||||
gpio_init(void)
|
||||
{
|
||||
int res;
|
||||
|
||||
/* do the formalities */
|
||||
|
||||
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
|
||||
if (res < 0) {
|
||||
printk(KERN_ERR "gpio: couldn't get a major number.\n");
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Clear all leds */
|
||||
CRIS_LED_NETWORK_GRP0_SET(0);
|
||||
CRIS_LED_NETWORK_GRP1_SET(0);
|
||||
CRIS_LED_ACTIVE_SET(0);
|
||||
CRIS_LED_DISK_READ(0);
|
||||
CRIS_LED_DISK_WRITE(0);
|
||||
|
||||
printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 "
|
||||
"Axis Communications AB\n");
|
||||
/* We call etrax_gpio_wake_up_check() from timer interrupt */
|
||||
if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
|
||||
IRQF_SHARED, "gpio poll", &alarmlist))
|
||||
printk(KERN_ERR "timer0 irq for gpio\n");
|
||||
|
||||
if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
|
||||
IRQF_SHARED, "gpio PA", &alarmlist))
|
||||
printk(KERN_ERR "PA irq for gpio\n");
|
||||
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
virtual_gpio_init();
|
||||
#endif
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/* this makes sure that gpio_init is called during kernel boot */
|
||||
|
||||
module_init(gpio_init);
|
|
@ -3,7 +3,6 @@
|
|||
#include <arch/dma.h>
|
||||
#include <arch/intmem.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
/* Functions for allocating DMA channels */
|
||||
EXPORT_SYMBOL(crisv32_request_dma);
|
||||
|
@ -20,8 +19,6 @@ EXPORT_SYMBOL(crisv32_pinmux_alloc);
|
|||
EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
|
||||
EXPORT_SYMBOL(crisv32_pinmux_dealloc);
|
||||
EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
|
||||
EXPORT_SYMBOL(crisv32_io_get_name);
|
||||
EXPORT_SYMBOL(crisv32_io_get);
|
||||
|
||||
/* Functions masking/unmasking interrupts */
|
||||
EXPORT_SYMBOL(crisv32_mask_irq);
|
||||
|
|
|
@ -77,8 +77,6 @@ static struct dbg_port *port =
|
|||
&ports[2];
|
||||
#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
|
||||
&ports[3];
|
||||
#elif defined(CONFIG_ETRAX_DEBUG_PORT4)
|
||||
&ports[4];
|
||||
#else
|
||||
NULL;
|
||||
#endif
|
||||
|
|
|
@ -292,11 +292,7 @@ _no_romfs_in_flash:
|
|||
;; For cramfs, partition starts with magic and length.
|
||||
;; For jffs2, a jhead is prepended which contains with magic and length.
|
||||
;; The jhead is not part of the jffs2 partition however.
|
||||
#ifndef CONFIG_ETRAXFS_SIM
|
||||
move.d __bss_start, $r0
|
||||
#else
|
||||
move.d __end, $r0
|
||||
#endif
|
||||
move.d [$r0], $r1
|
||||
cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
|
||||
beq 2f ; yes, jump
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
|
||||
#elif defined(CONFIG_ETRAX_KGDB_PORT1)
|
||||
#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
|
||||
#elif defined(CONFIG_ETRAX_KGB_PORT2)
|
||||
#elif defined(CONFIG_ETRAX_KGDB_PORT2)
|
||||
#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
|
||||
#elif defined(CONFIG_ETRAX_KGDB_PORT3)
|
||||
#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
|
||||
|
@ -464,14 +464,14 @@ init_IRQ(void)
|
|||
etrax_irv->v[i] = weird_irq;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
|
||||
domain = irq_domain_add_legacy(np, NR_IRQS - FIRST_IRQ,
|
||||
domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ,
|
||||
FIRST_IRQ, FIRST_IRQ,
|
||||
&crisv32_irq_ops, NULL);
|
||||
BUG_ON(!domain);
|
||||
irq_set_default_host(domain);
|
||||
of_node_put(np);
|
||||
|
||||
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
|
||||
for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT; i++, j++) {
|
||||
set_exception_vector(i, interrupt[j]);
|
||||
}
|
||||
|
||||
|
|
|
@ -384,19 +384,11 @@ int getDebugChar(void);
|
|||
/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
|
||||
void putDebugChar(int val);
|
||||
|
||||
/* Returns the integer equivalent of a hexadecimal character. */
|
||||
static int hex(char ch);
|
||||
|
||||
/* Convert the memory, pointed to by mem into hexadecimal representation.
|
||||
Put the result in buf, and return a pointer to the last character
|
||||
in buf (null). */
|
||||
static char *mem2hex(char *buf, unsigned char *mem, int count);
|
||||
|
||||
/* Convert the array, in hexadecimal representation, pointed to by buf into
|
||||
binary representation. Put the result in mem, and return a pointer to
|
||||
the character after the last byte written. */
|
||||
static unsigned char *hex2mem(unsigned char *mem, char *buf, int count);
|
||||
|
||||
/* Put the content of the array, in binary representation, pointed to by buf
|
||||
into memory pointed to by mem, and return a pointer to
|
||||
the character after the last byte written. */
|
||||
|
@ -449,7 +441,7 @@ static char output_buffer[BUFMAX];
|
|||
/* Error and warning messages. */
|
||||
enum error_type
|
||||
{
|
||||
SUCCESS, E01, E02, E03, E04, E05, E06,
|
||||
SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
|
||||
};
|
||||
|
||||
static char *error_message[] =
|
||||
|
@ -461,6 +453,8 @@ static char *error_message[] =
|
|||
"E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
|
||||
"E05 Change register content - P - the register is not implemented..",
|
||||
"E06 Change memory content - M - internal error.",
|
||||
"E07 Change register content - P - the register is not stored on the stack",
|
||||
"E08 Invalid parameter"
|
||||
};
|
||||
|
||||
/********************************** Breakpoint *******************************/
|
||||
|
@ -539,7 +533,7 @@ gdb_cris_strtol(const char *s, char **endptr, int base)
|
|||
/********************************* Register image ****************************/
|
||||
|
||||
/* Write a value to a specified register in the register image of the current
|
||||
thread. Returns status code SUCCESS, E02 or E05. */
|
||||
thread. Returns status code SUCCESS, E02, E05 or E08. */
|
||||
static int
|
||||
write_register(int regno, char *val)
|
||||
{
|
||||
|
@ -547,8 +541,9 @@ write_register(int regno, char *val)
|
|||
|
||||
if (regno >= R0 && regno <= ACR) {
|
||||
/* Consecutive 32-bit registers. */
|
||||
hex2mem((unsigned char *)®.r0 + (regno - R0) * sizeof(unsigned int),
|
||||
val, sizeof(unsigned int));
|
||||
if (hex2bin((unsigned char *)®.r0 + (regno - R0) * sizeof(unsigned int),
|
||||
val, sizeof(unsigned int)))
|
||||
status = E08;
|
||||
|
||||
} else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
|
||||
/* Read-only registers. */
|
||||
|
@ -557,16 +552,19 @@ write_register(int regno, char *val)
|
|||
} else if (regno == PID) {
|
||||
/* 32-bit register. (Even though we already checked SRS and WZ, we cannot
|
||||
combine this with the EXS - SPC write since SRS and WZ have different size.) */
|
||||
hex2mem((unsigned char *)®.pid, val, sizeof(unsigned int));
|
||||
if (hex2bin((unsigned char *)®.pid, val, sizeof(unsigned int)))
|
||||
status = E08;
|
||||
|
||||
} else if (regno == SRS) {
|
||||
/* 8-bit register. */
|
||||
hex2mem((unsigned char *)®.srs, val, sizeof(unsigned char));
|
||||
if (hex2bin((unsigned char *)®.srs, val, sizeof(unsigned char)))
|
||||
status = E08;
|
||||
|
||||
} else if (regno >= EXS && regno <= SPC) {
|
||||
/* Consecutive 32-bit registers. */
|
||||
hex2mem((unsigned char *)®.exs + (regno - EXS) * sizeof(unsigned int),
|
||||
val, sizeof(unsigned int));
|
||||
if (hex2bin((unsigned char *)®.exs + (regno - EXS) * sizeof(unsigned int),
|
||||
val, sizeof(unsigned int)))
|
||||
status = E08;
|
||||
|
||||
} else if (regno == PC) {
|
||||
/* Pseudo-register. Treat as read-only. */
|
||||
|
@ -574,7 +572,9 @@ write_register(int regno, char *val)
|
|||
|
||||
} else if (regno >= S0 && regno <= S15) {
|
||||
/* 32-bit registers. */
|
||||
hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int));
|
||||
if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int),
|
||||
val, sizeof(unsigned int)))
|
||||
status = E08;
|
||||
} else {
|
||||
/* Non-existing register. */
|
||||
status = E05;
|
||||
|
@ -630,19 +630,6 @@ read_register(char regno, unsigned int *valptr)
|
|||
}
|
||||
|
||||
/********************************** Packet I/O ******************************/
|
||||
/* Returns the integer equivalent of a hexadecimal character. */
|
||||
static int
|
||||
hex(char ch)
|
||||
{
|
||||
if ((ch >= 'a') && (ch <= 'f'))
|
||||
return (ch - 'a' + 10);
|
||||
if ((ch >= '0') && (ch <= '9'))
|
||||
return (ch - '0');
|
||||
if ((ch >= 'A') && (ch <= 'F'))
|
||||
return (ch - 'A' + 10);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Convert the memory, pointed to by mem into hexadecimal representation.
|
||||
Put the result in buf, and return a pointer to the last character
|
||||
in buf (null). */
|
||||
|
@ -689,22 +676,6 @@ mem2hex_nbo(char *buf, unsigned char *mem, int count)
|
|||
return buf;
|
||||
}
|
||||
|
||||
/* Convert the array, in hexadecimal representation, pointed to by buf into
|
||||
binary representation. Put the result in mem, and return a pointer to
|
||||
the character after the last byte written. */
|
||||
static unsigned char*
|
||||
hex2mem(unsigned char *mem, char *buf, int count)
|
||||
{
|
||||
int i;
|
||||
unsigned char ch;
|
||||
for (i = 0; i < count; i++) {
|
||||
ch = hex (*buf++) << 4;
|
||||
ch = ch + hex (*buf++);
|
||||
*mem++ = ch;
|
||||
}
|
||||
return mem;
|
||||
}
|
||||
|
||||
/* Put the content of the array, in binary representation, pointed to by buf
|
||||
into memory pointed to by mem, and return a pointer to the character after
|
||||
the last byte written.
|
||||
|
@ -763,8 +734,8 @@ getpacket(char *buffer)
|
|||
buffer[count] = 0;
|
||||
|
||||
if (ch == '#') {
|
||||
xmitcsum = hex(getDebugChar()) << 4;
|
||||
xmitcsum += hex(getDebugChar());
|
||||
xmitcsum = hex_to_bin(getDebugChar()) << 4;
|
||||
xmitcsum += hex_to_bin(getDebugChar());
|
||||
if (checksum != xmitcsum) {
|
||||
/* Wrong checksum */
|
||||
putDebugChar('-');
|
||||
|
@ -1304,14 +1275,17 @@ handle_exception(int sigval)
|
|||
/* Write registers. GXX..XX
|
||||
Each byte of register data is described by two hex digits.
|
||||
Success: OK
|
||||
Failure: void. */
|
||||
Failure: E08. */
|
||||
/* General and special registers. */
|
||||
hex2mem((char *)®, &input_buffer[1], sizeof(registers));
|
||||
if (hex2bin((char *)®, &input_buffer[1], sizeof(registers)))
|
||||
gdb_cris_strcpy(output_buffer, error_message[E08]);
|
||||
/* Support registers. */
|
||||
hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
|
||||
else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
|
||||
&input_buffer[1] + sizeof(registers),
|
||||
16 * sizeof(unsigned int));
|
||||
gdb_cris_strcpy(output_buffer, "OK");
|
||||
16 * sizeof(unsigned int)))
|
||||
gdb_cris_strcpy(output_buffer, error_message[E08]);
|
||||
else
|
||||
gdb_cris_strcpy(output_buffer, "OK");
|
||||
break;
|
||||
|
||||
case 'P':
|
||||
|
@ -1338,6 +1312,10 @@ handle_exception(int sigval)
|
|||
/* Do not support non-existing registers. */
|
||||
gdb_cris_strcpy(output_buffer, error_message[E05]);
|
||||
break;
|
||||
case E08:
|
||||
/* Invalid parameter. */
|
||||
gdb_cris_strcpy(output_buffer, error_message[E08]);
|
||||
break;
|
||||
default:
|
||||
/* Valid register number. */
|
||||
gdb_cris_strcpy(output_buffer, "OK");
|
||||
|
@ -1380,7 +1358,7 @@ handle_exception(int sigval)
|
|||
AA..AA is the start address, LLLL is the number of bytes, and
|
||||
XX..XX is the hexadecimal data.
|
||||
Success: OK
|
||||
Failure: void. */
|
||||
Failure: E08. */
|
||||
{
|
||||
char *lenptr;
|
||||
char *dataptr;
|
||||
|
@ -1389,13 +1367,15 @@ handle_exception(int sigval)
|
|||
int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
|
||||
if (*lenptr == ',' && *dataptr == ':') {
|
||||
if (input_buffer[0] == 'M') {
|
||||
hex2mem(addr, dataptr + 1, len);
|
||||
if (hex2bin(addr, dataptr + 1, len))
|
||||
gdb_cris_strcpy(output_buffer, error_message[E08]);
|
||||
else
|
||||
gdb_cris_strcpy(output_buffer, "OK");
|
||||
} else /* X */ {
|
||||
bin2mem(addr, dataptr + 1, len);
|
||||
gdb_cris_strcpy(output_buffer, "OK");
|
||||
}
|
||||
gdb_cris_strcpy(output_buffer, "OK");
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
gdb_cris_strcpy(output_buffer, error_message[E06]);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -128,10 +128,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
|
|||
{I2C_BOARD_INFO("tmp100", 0x4E)},
|
||||
#ifdef CONFIG_RTC_DRV_PCF8563
|
||||
{I2C_BOARD_INFO("pcf8563", 0x51)},
|
||||
#endif
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
{I2C_BOARD_INFO("vgpio", 0x20)},
|
||||
{I2C_BOARD_INFO("vgpio", 0x21)},
|
||||
#endif
|
||||
{I2C_BOARD_INFO("pca9536", 0x41)},
|
||||
{I2C_BOARD_INFO("fnp300", 0x40)},
|
||||
|
@ -146,10 +142,6 @@ static struct i2c_board_info __initdata i2c_info2[] = {
|
|||
{I2C_BOARD_INFO("tmp100", 0x4C)},
|
||||
{I2C_BOARD_INFO("tmp100", 0x4D)},
|
||||
{I2C_BOARD_INFO("tmp100", 0x4E)},
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
{I2C_BOARD_INFO("vgpio", 0x20)},
|
||||
{I2C_BOARD_INFO("vgpio", 0x21)},
|
||||
#endif
|
||||
{I2C_BOARD_INFO("pca9536", 0x41)},
|
||||
{I2C_BOARD_INFO("fnp300", 0x40)},
|
||||
{I2C_BOARD_INFO("fnp300", 0x42)},
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := dma.o pinmux.o io.o arbiter.o
|
||||
obj-y := dma.o pinmux.o arbiter.o
|
||||
|
||||
clean:
|
||||
|
||||
|
|
|
@ -1,149 +0,0 @@
|
|||
/*
|
||||
* Helper functions for I/O pins.
|
||||
*
|
||||
* Copyright (c) 2005-2007 Axis Communications AB.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
|
||||
struct crisv32_ioport crisv32_ioports[] = {
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
|
||||
32
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
|
||||
32
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
|
||||
16
|
||||
},
|
||||
};
|
||||
|
||||
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
|
||||
|
||||
struct crisv32_iopin crisv32_led_net0_green;
|
||||
struct crisv32_iopin crisv32_led_net0_red;
|
||||
struct crisv32_iopin crisv32_led2_green;
|
||||
struct crisv32_iopin crisv32_led2_red;
|
||||
struct crisv32_iopin crisv32_led3_green;
|
||||
struct crisv32_iopin crisv32_led3_red;
|
||||
|
||||
/* Dummy port used when green LED and red LED is on the same bit */
|
||||
static unsigned long io_dummy;
|
||||
static struct crisv32_ioport dummy_port = {
|
||||
&io_dummy,
|
||||
&io_dummy,
|
||||
&io_dummy,
|
||||
32
|
||||
};
|
||||
static struct crisv32_iopin dummy_led = {
|
||||
&dummy_port,
|
||||
0
|
||||
};
|
||||
|
||||
static int __init crisv32_io_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
u32 i;
|
||||
|
||||
/* Locks *should* be dynamically initialized. */
|
||||
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
|
||||
spin_lock_init(&crisv32_ioports[i].lock);
|
||||
spin_lock_init(&dummy_port.lock);
|
||||
|
||||
/* Initialize LEDs */
|
||||
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
|
||||
ret += crisv32_io_get_name(&crisv32_led_net0_green,
|
||||
CONFIG_ETRAX_LED_G_NET0);
|
||||
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
|
||||
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
|
||||
ret += crisv32_io_get_name(&crisv32_led_net0_red,
|
||||
CONFIG_ETRAX_LED_R_NET0);
|
||||
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
|
||||
} else
|
||||
crisv32_led_net0_red = dummy_led;
|
||||
#endif
|
||||
|
||||
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
|
||||
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
|
||||
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
|
||||
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
|
||||
|
||||
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
__initcall(crisv32_io_init);
|
||||
|
||||
int crisv32_io_get(struct crisv32_iopin *iopin,
|
||||
unsigned int port, unsigned int pin)
|
||||
{
|
||||
if (port > NBR_OF_PORTS)
|
||||
return -EINVAL;
|
||||
if (port > crisv32_ioports[port].pin_count)
|
||||
return -EINVAL;
|
||||
|
||||
iopin->bit = 1 << pin;
|
||||
iopin->port = &crisv32_ioports[port];
|
||||
|
||||
if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
|
||||
{
|
||||
int port;
|
||||
int pin;
|
||||
|
||||
if (toupper(*name) == 'P')
|
||||
name++;
|
||||
|
||||
if (toupper(*name) < 'A' || toupper(*name) > 'E')
|
||||
return -EINVAL;
|
||||
|
||||
port = toupper(*name) - 'A';
|
||||
name++;
|
||||
pin = simple_strtoul(name, NULL, 10);
|
||||
|
||||
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
|
||||
return -EINVAL;
|
||||
|
||||
iopin->bit = 1 << pin;
|
||||
iopin->port = &crisv32_ioports[port];
|
||||
|
||||
if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI I/O access stuff */
|
||||
struct cris_io_operations *cris_iops = NULL;
|
||||
EXPORT_SYMBOL(cris_iops);
|
||||
#endif
|
||||
|
|
@ -192,25 +192,6 @@ config ETRAX_DEF_GIO_PE_OUT
|
|||
Configures the initial data for the general port E bits. Most
|
||||
products should use 00000 here.
|
||||
|
||||
config ETRAX_DEF_GIO_PV_OE
|
||||
hex "GIO_PV_OE"
|
||||
depends on ETRAX_VIRTUAL_GPIO
|
||||
default "0000"
|
||||
help
|
||||
Configures the direction of virtual general port V bits. 1 is out,
|
||||
0 is in. This is often totally different depending on the product
|
||||
used. These bits are used for all kinds of stuff. If you don't know
|
||||
what to use, it is always safe to put all as inputs, although
|
||||
floating inputs isn't good.
|
||||
|
||||
config ETRAX_DEF_GIO_PV_OUT
|
||||
hex "GIO_PV_OUT"
|
||||
depends on ETRAX_VIRTUAL_GPIO
|
||||
default "0000"
|
||||
help
|
||||
Configures the initial data for the virtual general port V bits.
|
||||
Most products should use 0000 here.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := dma.o pinmux.o io.o arbiter.o
|
||||
obj-y := dma.o pinmux.o arbiter.o
|
||||
|
||||
clean:
|
||||
|
||||
|
|
|
@ -1,191 +0,0 @@
|
|||
/*
|
||||
* Helper functions for I/O pins.
|
||||
*
|
||||
* Copyright (c) 2004-2007 Axis Communications AB.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
|
||||
#ifndef DEBUG
|
||||
#define DEBUG(x)
|
||||
#endif
|
||||
|
||||
struct crisv32_ioport crisv32_ioports[] = {
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
|
||||
8
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
|
||||
18
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
|
||||
18
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
|
||||
18
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
|
||||
18
|
||||
}
|
||||
};
|
||||
|
||||
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
|
||||
|
||||
struct crisv32_iopin crisv32_led_net0_green;
|
||||
struct crisv32_iopin crisv32_led_net0_red;
|
||||
struct crisv32_iopin crisv32_led_net1_green;
|
||||
struct crisv32_iopin crisv32_led_net1_red;
|
||||
struct crisv32_iopin crisv32_led2_green;
|
||||
struct crisv32_iopin crisv32_led2_red;
|
||||
struct crisv32_iopin crisv32_led3_green;
|
||||
struct crisv32_iopin crisv32_led3_red;
|
||||
|
||||
/* Dummy port used when green LED and red LED is on the same bit */
|
||||
static unsigned long io_dummy;
|
||||
static struct crisv32_ioport dummy_port = {
|
||||
&io_dummy,
|
||||
&io_dummy,
|
||||
&io_dummy,
|
||||
18
|
||||
};
|
||||
static struct crisv32_iopin dummy_led = {
|
||||
&dummy_port,
|
||||
0
|
||||
};
|
||||
|
||||
static int __init crisv32_io_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
u32 i;
|
||||
|
||||
/* Locks *should* be dynamically initialized. */
|
||||
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
|
||||
spin_lock_init(&crisv32_ioports[i].lock);
|
||||
spin_lock_init(&dummy_port.lock);
|
||||
|
||||
/* Initialize LEDs */
|
||||
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
|
||||
ret +=
|
||||
crisv32_io_get_name(&crisv32_led_net0_green,
|
||||
CONFIG_ETRAX_LED_G_NET0);
|
||||
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
|
||||
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
|
||||
ret +=
|
||||
crisv32_io_get_name(&crisv32_led_net0_red,
|
||||
CONFIG_ETRAX_LED_R_NET0);
|
||||
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
|
||||
} else
|
||||
crisv32_led_net0_red = dummy_led;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
|
||||
ret +=
|
||||
crisv32_io_get_name(&crisv32_led_net1_green,
|
||||
CONFIG_ETRAX_LED_G_NET1);
|
||||
crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
|
||||
if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
|
||||
crisv32_io_get_name(&crisv32_led_net1_red,
|
||||
CONFIG_ETRAX_LED_R_NET1);
|
||||
crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
|
||||
} else
|
||||
crisv32_led_net1_red = dummy_led;
|
||||
#endif
|
||||
|
||||
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
|
||||
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
|
||||
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
|
||||
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
|
||||
|
||||
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
__initcall(crisv32_io_init);
|
||||
|
||||
int crisv32_io_get(struct crisv32_iopin *iopin,
|
||||
unsigned int port, unsigned int pin)
|
||||
{
|
||||
if (port > NBR_OF_PORTS)
|
||||
return -EINVAL;
|
||||
if (port > crisv32_ioports[port].pin_count)
|
||||
return -EINVAL;
|
||||
|
||||
iopin->bit = 1 << pin;
|
||||
iopin->port = &crisv32_ioports[port];
|
||||
|
||||
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
|
||||
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
|
||||
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
|
||||
return -EIO;
|
||||
DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
|
||||
pin, port));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
|
||||
{
|
||||
int port;
|
||||
int pin;
|
||||
|
||||
if (toupper(*name) == 'P')
|
||||
name++;
|
||||
|
||||
if (toupper(*name) < 'A' || toupper(*name) > 'E')
|
||||
return -EINVAL;
|
||||
|
||||
port = toupper(*name) - 'A';
|
||||
name++;
|
||||
pin = simple_strtoul(name, NULL, 10);
|
||||
|
||||
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
|
||||
return -EINVAL;
|
||||
|
||||
iopin->bit = 1 << pin;
|
||||
iopin->port = &crisv32_ioports[port];
|
||||
|
||||
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
|
||||
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
|
||||
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
|
||||
return -EIO;
|
||||
|
||||
DEBUG(printk(KERN_DEBUG
|
||||
"crisv32_io_get_name: Allocated pin %d on port %d\n",
|
||||
pin, port));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI I/O access stuff */
|
||||
struct cris_io_operations *cris_iops = NULL;
|
||||
EXPORT_SYMBOL(cris_iops);
|
||||
#endif
|
46
arch/cris/boot/dts/artpec3.dtsi
Normal file
46
arch/cris/boot/dts/artpec3.dtsi
Normal file
|
@ -0,0 +1,46 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "axis,crisv32";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
model = "artpec3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "axis,crisv32-intc";
|
||||
reg = <0xb002a000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gio: gpio@b0020000 {
|
||||
compatible = "axis,artpec3-gio";
|
||||
reg = <0xb0020000 0x1000>;
|
||||
interrupts = <61>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <3>;
|
||||
};
|
||||
|
||||
serial@b003e000 {
|
||||
compatible = "axis,etraxfs-uart";
|
||||
reg = <0xb003e000 0x1000>;
|
||||
interrupts = <64>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -1,5 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/include/ "etraxfs.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -15,4 +17,51 @@
|
|||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio-sck = <&gio 1 0 0xd>;
|
||||
gpio-miso = <&gio 4 0 0xd>;
|
||||
gpio-mosi = <&gio 0 0 0xd>;
|
||||
cs-gpios = <&gio 3 0 0xd>;
|
||||
num-chipselects = <1>;
|
||||
|
||||
temp-sensor@0 {
|
||||
compatible = "ti,lm70";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&gio 5 0 0xd>, <&gio 6 0 0xd>;
|
||||
i2c-gpio,delay-us = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
network {
|
||||
label = "network";
|
||||
gpios = <&gio 2 GPIO_ACTIVE_LOW 0xa>;
|
||||
};
|
||||
|
||||
status {
|
||||
label = "status";
|
||||
gpios = <&gio 3 GPIO_ACTIVE_LOW 0xa>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -28,6 +28,14 @@
|
|||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gio: gpio@b001a000 {
|
||||
compatible = "axis,etraxfs-gio";
|
||||
reg = <0xb001a000 0x1000>;
|
||||
interrupts = <50>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <3>;
|
||||
};
|
||||
|
||||
serial@b00260000 {
|
||||
compatible = "axis,etraxfs-uart";
|
||||
reg = <0xb0026000 0x1000>;
|
||||
|
|
1
arch/cris/boot/dts/include/dt-bindings
Symbolic link
1
arch/cris/boot/dts/include/dt-bindings
Symbolic link
|
@ -0,0 +1 @@
|
|||
../../../../../include/dt-bindings
|
76
arch/cris/boot/dts/p1343.dts
Normal file
76
arch/cris/boot/dts/p1343.dts
Normal file
|
@ -0,0 +1,76 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/include/ "artpec3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Axis P1343 Network Camera";
|
||||
compatible = "axis,p1343";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
soc {
|
||||
uart0: serial@b003e000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&gio 3 0 0xa>, <&gio 2 0 0xa>;
|
||||
i2c-gpio,delay-us = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "status:green";
|
||||
gpios = <&gio 0 GPIO_ACTIVE_LOW 0xc>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "status:red";
|
||||
gpios = <&gio 1 GPIO_ACTIVE_LOW 0xc>;
|
||||
};
|
||||
|
||||
network_green {
|
||||
label = "network:green";
|
||||
gpios = <&gio 2 GPIO_ACTIVE_LOW 0xc>;
|
||||
};
|
||||
|
||||
network_red {
|
||||
label = "network:red";
|
||||
gpios = <&gio 3 GPIO_ACTIVE_LOW 0xc>;
|
||||
};
|
||||
|
||||
power_red {
|
||||
label = "power:red";
|
||||
gpios = <&gio 4 GPIO_ACTIVE_LOW 0xc>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
activity-button@0 {
|
||||
label = "Activity Button";
|
||||
linux,code = <KEY_FN>;
|
||||
gpios = <&gio 13 GPIO_ACTIVE_LOW 0xd>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -281,9 +281,6 @@ wait_ser:
|
|||
#ifdef CONFIG_ETRAX_PB_LEDS
|
||||
move.b $r2, [R_PORT_PB_DATA]
|
||||
#endif
|
||||
#ifdef CONFIG_ETRAX_90000000_LEDS
|
||||
move.b $r2, [0x90000000]
|
||||
#endif
|
||||
#endif
|
||||
|
||||
;; check if we got something on the serial port
|
||||
|
|
|
@ -1,140 +0,0 @@
|
|||
#ifndef _ASM_ARCH_CRIS_IO_H
|
||||
#define _ASM_ARCH_CRIS_IO_H
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <hwregs/reg_map.h>
|
||||
#include <hwregs/reg_rdwr.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
|
||||
enum crisv32_io_dir
|
||||
{
|
||||
crisv32_io_dir_in = 0,
|
||||
crisv32_io_dir_out = 1
|
||||
};
|
||||
|
||||
struct crisv32_ioport
|
||||
{
|
||||
volatile unsigned long *oe;
|
||||
volatile unsigned long *data;
|
||||
volatile unsigned long *data_in;
|
||||
unsigned int pin_count;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct crisv32_iopin
|
||||
{
|
||||
struct crisv32_ioport* port;
|
||||
int bit;
|
||||
};
|
||||
|
||||
extern struct crisv32_ioport crisv32_ioports[];
|
||||
|
||||
extern struct crisv32_iopin crisv32_led1_green;
|
||||
extern struct crisv32_iopin crisv32_led1_red;
|
||||
extern struct crisv32_iopin crisv32_led2_green;
|
||||
extern struct crisv32_iopin crisv32_led2_red;
|
||||
extern struct crisv32_iopin crisv32_led3_green;
|
||||
extern struct crisv32_iopin crisv32_led3_red;
|
||||
|
||||
extern struct crisv32_iopin crisv32_led_net0_green;
|
||||
extern struct crisv32_iopin crisv32_led_net0_red;
|
||||
extern struct crisv32_iopin crisv32_led_net1_green;
|
||||
extern struct crisv32_iopin crisv32_led_net1_red;
|
||||
|
||||
static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
|
||||
{
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&iopin->port->lock, flags);
|
||||
|
||||
if (iopin->port->data) {
|
||||
if (val)
|
||||
*iopin->port->data |= iopin->bit;
|
||||
else
|
||||
*iopin->port->data &= ~iopin->bit;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&iopin->port->lock, flags);
|
||||
}
|
||||
|
||||
static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
|
||||
enum crisv32_io_dir dir)
|
||||
{
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&iopin->port->lock, flags);
|
||||
|
||||
if (iopin->port->oe) {
|
||||
if (dir == crisv32_io_dir_in)
|
||||
*iopin->port->oe &= ~iopin->bit;
|
||||
else
|
||||
*iopin->port->oe |= iopin->bit;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&iopin->port->lock, flags);
|
||||
}
|
||||
|
||||
static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
|
||||
{
|
||||
return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
|
||||
}
|
||||
|
||||
int crisv32_io_get(struct crisv32_iopin* iopin,
|
||||
unsigned int port, unsigned int pin);
|
||||
int crisv32_io_get_name(struct crisv32_iopin* iopin,
|
||||
const char *name);
|
||||
|
||||
#define CRIS_LED_OFF 0x00
|
||||
#define CRIS_LED_GREEN 0x01
|
||||
#define CRIS_LED_RED 0x02
|
||||
#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
|
||||
|
||||
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
|
||||
#define CRIS_LED_NETWORK_GRP0_SET(x) \
|
||||
do { \
|
||||
CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \
|
||||
CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \
|
||||
} while (0)
|
||||
#else
|
||||
#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {}
|
||||
#endif
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP0_SET_G(x) \
|
||||
crisv32_io_set(&crisv32_led_net0_green, !(x));
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP0_SET_R(x) \
|
||||
crisv32_io_set(&crisv32_led_net0_red, !(x));
|
||||
|
||||
#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
|
||||
#define CRIS_LED_NETWORK_GRP1_SET(x) \
|
||||
do { \
|
||||
CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \
|
||||
CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \
|
||||
} while (0)
|
||||
#else
|
||||
#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {}
|
||||
#endif
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP1_SET_G(x) \
|
||||
crisv32_io_set(&crisv32_led_net1_green, !(x));
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP1_SET_R(x) \
|
||||
crisv32_io_set(&crisv32_led_net1_red, !(x));
|
||||
|
||||
#define CRIS_LED_ACTIVE_SET(x) \
|
||||
do { \
|
||||
CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
|
||||
CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
|
||||
} while (0)
|
||||
|
||||
#define CRIS_LED_ACTIVE_SET_G(x) \
|
||||
crisv32_io_set(&crisv32_led2_green, !(x));
|
||||
#define CRIS_LED_ACTIVE_SET_R(x) \
|
||||
crisv32_io_set(&crisv32_led2_red, !(x));
|
||||
#define CRIS_LED_DISK_WRITE(x) \
|
||||
do{\
|
||||
crisv32_io_set(&crisv32_led3_green, !(x)); \
|
||||
crisv32_io_set(&crisv32_led3_red, !(x)); \
|
||||
}while(0)
|
||||
#define CRIS_LED_DISK_READ(x) \
|
||||
crisv32_io_set(&crisv32_led3_green, !(x));
|
||||
|
||||
#endif
|
|
@ -4,7 +4,7 @@
|
|||
#include <hwregs/intr_vect.h>
|
||||
|
||||
/* Number of non-cpu interrupts. */
|
||||
#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */
|
||||
#define NR_IRQS (NBR_INTR_VECT + 256) /* Exceptions + IRQs */
|
||||
#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
|
||||
#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
|
||||
#if NR_REAL_IRQS > 32
|
||||
|
|
|
@ -45,8 +45,7 @@
|
|||
assumed that we want to share code when debugging (exposes more
|
||||
trouble). */
|
||||
#ifndef SHARE_LIB_CORE
|
||||
# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \
|
||||
&& !defined(CONFIG_SHARE_SHLIB_CORE)
|
||||
# if (defined(__KERNEL__) || !defined(RELOC_DEBUG))
|
||||
# define SHARE_LIB_CORE 0
|
||||
# else
|
||||
# define SHARE_LIB_CORE 1
|
||||
|
|
|
@ -2,7 +2,9 @@
|
|||
#define _ASM_CRIS_IO_H
|
||||
|
||||
#include <asm/page.h> /* for __va, __pa */
|
||||
#ifdef CONFIG_ETRAX_ARCH_V10
|
||||
#include <arch/io.h>
|
||||
#endif
|
||||
#include <asm-generic/iomap.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
|
|
|
@ -11,26 +11,6 @@
|
|||
* g1-g7 and g25-g31 is both input and outputs but on different pins
|
||||
* Also note that some bits change pins depending on what interfaces
|
||||
* are enabled.
|
||||
*
|
||||
* For ETRAX FS (CONFIG_ETRAXFS):
|
||||
* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
|
||||
* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
|
||||
* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
|
||||
* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
|
||||
* /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
|
||||
* /dev/leds minor 2, Access to leds depending on kernelconfig
|
||||
*
|
||||
* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
|
||||
* /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
|
||||
* /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
|
||||
* /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
|
||||
* /dev/gpiod minor 4, 32 bit GPIO, input only
|
||||
* /dev/leds minor 2, Access to leds depending on kernelconfig
|
||||
* /dev/pwm0 minor 16, PWM channel 0 on PA30
|
||||
* /dev/pwm1 minor 17, PWM channel 1 on PA31
|
||||
* /dev/pwm2 minor 18, PWM channel 2 on PB26
|
||||
* /dev/ppwm minor 19, PPWM channel
|
||||
*
|
||||
*/
|
||||
#ifndef _ASM_ETRAXGPIO_H
|
||||
#define _ASM_ETRAXGPIO_H
|
||||
|
@ -40,52 +20,12 @@
|
|||
#define ETRAXGPIO_IOCTYPE 43
|
||||
|
||||
/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
|
||||
#ifdef CONFIG_ETRAX_ARCH_V10
|
||||
#define GPIO_MINOR_A 0
|
||||
#define GPIO_MINOR_B 1
|
||||
#define GPIO_MINOR_LEDS 2
|
||||
#define GPIO_MINOR_G 3
|
||||
#define GPIO_MINOR_LAST 3
|
||||
#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ETRAXFS
|
||||
#define GPIO_MINOR_A 0
|
||||
#define GPIO_MINOR_B 1
|
||||
#define GPIO_MINOR_LEDS 2
|
||||
#define GPIO_MINOR_C 3
|
||||
#define GPIO_MINOR_D 4
|
||||
#define GPIO_MINOR_E 5
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
#define GPIO_MINOR_V 6
|
||||
#define GPIO_MINOR_LAST 6
|
||||
#else
|
||||
#define GPIO_MINOR_LAST 5
|
||||
#endif
|
||||
#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CRIS_MACH_ARTPEC3
|
||||
#define GPIO_MINOR_A 0
|
||||
#define GPIO_MINOR_B 1
|
||||
#define GPIO_MINOR_LEDS 2
|
||||
#define GPIO_MINOR_C 3
|
||||
#define GPIO_MINOR_D 4
|
||||
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
||||
#define GPIO_MINOR_V 6
|
||||
#define GPIO_MINOR_LAST 6
|
||||
#else
|
||||
#define GPIO_MINOR_LAST 4
|
||||
#endif
|
||||
#define GPIO_MINOR_FIRST_PWM 16
|
||||
#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
|
||||
#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
|
||||
#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
|
||||
#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
|
||||
#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
|
||||
#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* supported ioctl _IOC_NR's */
|
||||
|
@ -139,101 +79,4 @@
|
|||
#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
|
||||
/* *arg updated with current output pins. */
|
||||
|
||||
/* The following ioctl's are applicable to the PWM channels only */
|
||||
|
||||
#define IO_PWM_SET_MODE 0x20
|
||||
|
||||
enum io_pwm_mode {
|
||||
PWM_OFF = 0, /* disabled, deallocated */
|
||||
PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
|
||||
PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
|
||||
PWM_VARFREQ = 3, /* individually configurable high/low periods */
|
||||
PWM_SOFT = 4 /* software generated */
|
||||
};
|
||||
|
||||
struct io_pwm_set_mode {
|
||||
enum io_pwm_mode mode;
|
||||
};
|
||||
|
||||
/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
|
||||
* from 10ns (value = 0) to 81920ns (value = 8191)
|
||||
* (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
|
||||
* 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
|
||||
* cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
|
||||
*/
|
||||
#define IO_PWM_SET_PERIOD 0x21
|
||||
|
||||
struct io_pwm_set_period {
|
||||
unsigned int lo; /* 0..8191 */
|
||||
unsigned int hi; /* 0..8191 */
|
||||
};
|
||||
|
||||
/* Only for modes PWM_STANDARD and PWM_FAST.
|
||||
* For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
|
||||
* 0 (value = 0) to 255/256 (value = 255).
|
||||
* For PWM_FAST, set duty cycle of PWM output signal from
|
||||
* 0% (value = 0) to 100% (value = 255). Output signal in this mode
|
||||
* is a 10ns pulse surrounded by a high or low level depending on duty
|
||||
* cycle (except for 0% and 100% which result in a constant output).
|
||||
* Resulting output frequency varies from 50 MHz at 50% duty cycle,
|
||||
* down to 390 kHz at min/max duty cycle.
|
||||
*/
|
||||
#define IO_PWM_SET_DUTY 0x22
|
||||
|
||||
struct io_pwm_set_duty {
|
||||
int duty; /* 0..255 */
|
||||
};
|
||||
|
||||
/* Returns information about the latest PWM pulse.
|
||||
* lo: Length of the latest low period, in units of 10ns.
|
||||
* hi: Length of the latest high period, in units of 10ns.
|
||||
* cnt: Time since last detected edge, in units of 10ns.
|
||||
*
|
||||
* The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
|
||||
*
|
||||
* NOTE: All PWM devices is connected to the same input source.
|
||||
*/
|
||||
#define IO_PWM_GET_PERIOD 0x23
|
||||
|
||||
struct io_pwm_get_period {
|
||||
unsigned int lo;
|
||||
unsigned int hi;
|
||||
unsigned int cnt;
|
||||
};
|
||||
|
||||
/* Sets the input source for the PWM input. For the src value see the
|
||||
* register description for gio:rw_pwm_in_cfg.
|
||||
*
|
||||
* NOTE: All PWM devices is connected to the same input source.
|
||||
*/
|
||||
#define IO_PWM_SET_INPUT_SRC 0x24
|
||||
struct io_pwm_set_input_src {
|
||||
unsigned int src; /* 0..7 */
|
||||
};
|
||||
|
||||
/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
|
||||
#define IO_PPWM_SET_DUTY 0x25
|
||||
|
||||
struct io_ppwm_set_duty {
|
||||
int duty; /* 0..255 */
|
||||
};
|
||||
|
||||
/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
|
||||
* PWM capable gpio pins:
|
||||
*/
|
||||
#define IO_PWMCLK_SETGET_CONFIG 0x26
|
||||
struct gpio_pwmclk_conf {
|
||||
unsigned int gpiopin; /* The pin number based on the opened device */
|
||||
unsigned int baseclk; /* The base clock to use, or sw will select one close*/
|
||||
unsigned int low; /* The number of low periods of the baseclk */
|
||||
unsigned int high; /* The number of high periods of the baseclk */
|
||||
};
|
||||
|
||||
/* Examples:
|
||||
* To get a symmetric 12 MHz clock without knowing anything about the hardware:
|
||||
* baseclk = 12000000, low = 0, high = 0
|
||||
* To just get info of current setting:
|
||||
* baseclk = 0, low = 0, high = 0, the values will be updated by driver.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
|
|
@ -18,7 +18,6 @@
|
|||
#include <asm/pgtable.h>
|
||||
#include <asm/fasttimer.h>
|
||||
|
||||
extern unsigned long get_cmos_time(void);
|
||||
extern void __Udiv(void);
|
||||
extern void __Umod(void);
|
||||
extern void __Div(void);
|
||||
|
@ -30,7 +29,6 @@ extern void __negdi2(void);
|
|||
extern void iounmap(volatile void * __iomem);
|
||||
|
||||
/* Platform dependent support */
|
||||
EXPORT_SYMBOL(get_cmos_time);
|
||||
EXPORT_SYMBOL(loops_per_usec);
|
||||
|
||||
/* Math functions */
|
||||
|
|
|
@ -39,31 +39,6 @@
|
|||
extern unsigned long loops_per_jiffy; /* init/main.c */
|
||||
unsigned long loops_per_usec;
|
||||
|
||||
int set_rtc_mmss(unsigned long nowtime)
|
||||
{
|
||||
D(printk(KERN_DEBUG "set_rtc_mmss(%lu)\n", nowtime));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* grab the time from the RTC chip */
|
||||
unsigned long get_cmos_time(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int update_persistent_clock(struct timespec now)
|
||||
{
|
||||
return set_rtc_mmss(now.tv_sec);
|
||||
}
|
||||
|
||||
void read_persistent_clock(struct timespec *ts)
|
||||
{
|
||||
ts->tv_sec = 0;
|
||||
ts->tv_nsec = 0;
|
||||
}
|
||||
|
||||
|
||||
extern void cris_profile_sample(struct pt_regs* regs);
|
||||
|
||||
void
|
||||
|
|
Loading…
Reference in a new issue