intel-iommu: Use domain_pfn_mapping() in __intel_map_single()
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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61df744314
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0ab36de274
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@ -2477,14 +2477,12 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
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return 0;
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iommu = domain_get_iommu(domain);
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size = aligned_size((u64)paddr, size);
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size = aligned_size(paddr, size) >> VTD_PAGE_SHIFT;
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iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
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iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT, pdev->dma_mask);
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if (!iova)
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goto error;
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start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
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/*
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* Check if DMAR supports zero-length reads on write only
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* mappings..
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@ -2500,20 +2498,20 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
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* might have two guest_addr mapping to the same host paddr, but this
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* is not a big problem
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*/
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ret = domain_page_mapping(domain, start_paddr,
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((u64)paddr) & PHYSICAL_PAGE_MASK,
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size, prot);
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ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
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paddr >> VTD_PAGE_SHIFT, size, prot);
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if (ret)
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goto error;
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start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
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/* it's a non-present to present mapping. Only flush if caching mode */
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if (cap_caching_mode(iommu->cap))
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iommu_flush_iotlb_psi(iommu, 0, start_paddr,
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size >> VTD_PAGE_SHIFT);
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iommu_flush_iotlb_psi(iommu, 0, start_paddr, size);
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else
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iommu_flush_write_buffer(iommu);
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return start_paddr + ((u64)paddr & (~PAGE_MASK));
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return start_paddr + (paddr & (~PAGE_MASK));
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error:
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if (iova)
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