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MLK-16938 ARM64: dts: imx8: refine the imx8 dts 

- Add the clk_req property for imx8 pcie, make sure that
the clk_req would be active.
- Correct the spell mistake of pcie pinctrl on imx8qxp.
- Fix the potential conflication with the usage of SC MU,
remove the useless "fsl,imx8-mu" of rpmsg.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
pull/10/head
Richard Zhu 2017-11-22 16:24:03 +08:00 committed by Jason Liu
parent 3807aad9e4
commit 0abd8e765b
6 changed files with 10 additions and 6 deletions
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4
Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
View File

@ -17,7 +17,7 @@ message unit module for RPMSG
- mu_rpmsg : The message unit module used to do the communications
between the asymmetric cores.
- compatible : "fsl,imx8-mu", "fsl,imx6sx-mu", "fsl,imx-mu-rpmsg1".
- compatible : "fsl,imx6sx-mu", "fsl,imx-mu-rpmsg1".
Different mu module would be used by the different remote processor.
The "fsl, imx6sx-mu" is used by the first remote processor.
The "fsl,imx-mu-rpmsg1" is used by the second remote process.
@ -46,7 +46,7 @@ imx_rpmsg: imx_rpmsg {
ranges;
mu_rpmsg: mu_rpmsg@37440000 {
compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
compatible = "fsl,imx6sx-mu";
reg = <0x0 0x37440000 0x0 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm40>;

2
arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
View File

@ -827,6 +827,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pciea>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -835,6 +836,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>;
clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
View File

@ -633,6 +633,7 @@
pinctrl-0 = <&pinctrl_pciea>;
disable-gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
epdev_on-supply = <&epdev_on>;
status = "okay";
};

4
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
View File

@ -3135,7 +3135,7 @@
ranges;
mu_rpmsg: mu_rpmsg@37440000 {
compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
compatible = "fsl,imx6sx-mu";
reg = <0x0 0x37440000 0x0 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm40>;
@ -3151,7 +3151,7 @@
};
mu_rpmsg1: mu_rpmsg1@3b440000 {
compatible = "fsl,imx8-mu", "fsl,imx-mu-rpmsg1";
compatible = "fsl,imx-mu-rpmsg1";
reg = <0x0 0x3b440000 0x0 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm41>;

3
arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
View File

@ -366,7 +366,7 @@
>;
};
pinctrl_pcieb: pcieagrp{
pinctrl_pcieb: pciebgrp{
fsl,pins = <
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
@ -603,6 +603,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
View File

@ -2349,7 +2349,7 @@
ranges;
mu_rpmsg: mu_rpmsg@37440000 {
compatible = "fsl,imx8-mu", "fsl,imx6sx-mu";
compatible = "fsl,imx6sx-mu";
reg = <0x0 0x37440000 0x0 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm40>;