[PATCH] m68knommu: read/write register access for ColdFire core timer
Modify the m68knommu/ColdFire core timer code to use register offsets with raw_read/raw_write access, instead of a mapped struct. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>wifi-calibration
Greg Ungerer
Linus Torvalds
parent
c88b36e2c8
commit
0b7ac8e479
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@ -14,6 +14,7 @@
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#include <linux/param.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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@ -23,6 +24,11 @@
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/***************************************************************************/
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/*
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* By default use timer1 as the system clock timer.
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*/
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#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
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/*
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* Default the timer and vector to use for ColdFire. Some ColdFire
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* CPU's and some boards may want different. Their sub-architecture
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@ -32,8 +38,6 @@ unsigned int mcf_timervector = 29;
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unsigned int mcf_profilevector = 31;
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unsigned int mcf_timerlevel = 5;
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static volatile struct mcftimer *mcf_timerp;
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/*
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* These provide the underlying interrupt vector support.
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* Unfortunately it is a little different on each ColdFire.
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@ -46,20 +50,17 @@ extern int mcf_timerirqpending(int timer);
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void coldfire_tick(void)
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{
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/* Reset the ColdFire timer */
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mcf_timerp->ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
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}
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/***************************************************************************/
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void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *))
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{
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/* Set up an internal TIMER as poll clock */
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mcf_timerp = (volatile struct mcftimer *) (MCF_MBAR + MCFTIMER_BASE1);
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mcf_timerp->tmr = MCFTIMER_TMR_DISABLE;
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mcf_timerp->trr = (unsigned short) ((MCF_BUSCLK / 16) / HZ);
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mcf_timerp->tmr = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
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__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
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__raw_writew(((MCF_BUSCLK / 16) / HZ), TA(MCFTIMER_TRR));
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__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
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request_irq(mcf_timervector, handler, SA_INTERRUPT, "timer", NULL);
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mcf_settimericr(1, mcf_timerlevel);
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@ -75,13 +76,8 @@ unsigned long coldfire_timer_offset(void)
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{
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unsigned long trr, tcn, offset;
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/*
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* The change to pointer and de-reference is to force the compiler
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* to read the registers with a single 16bit access. Otherwise it
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* does some crazy 8bit read combining.
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*/
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tcn = *(&mcf_timerp->tcn);
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trr = *(&mcf_timerp->trr);
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tcn = __raw_readw(TA(MCFTIMER_TCN));
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trr = __raw_readw(TA(MCFTIMER_TRR));
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offset = (tcn * (1000000 / HZ)) / trr;
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/* Check if we just wrapped the counters and maybe missed a tick */
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@ -94,22 +90,24 @@ unsigned long coldfire_timer_offset(void)
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#ifdef CONFIG_HIGHPROFILE
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/***************************************************************************/
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/*
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* By default use timer2 as the profiler clock timer.
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*/
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#define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a))
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/*
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* Choose a reasonably fast profile timer. Make it an odd value to
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* try and get good coverage of kernal operations.
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*/
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#define PROFILEHZ 1013
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static volatile struct mcftimer *mcf_proftp;
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/*
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* Use the other timer to provide high accuracy profiling info.
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*/
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void coldfire_profile_tick(int irq, void *dummy, struct pt_regs *regs)
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{
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/* Reset ColdFire timer2 */
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mcf_proftp->ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
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if (current->pid)
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profile_tick(CPU_PROFILING, regs);
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}
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@ -121,12 +119,11 @@ void coldfire_profile_init(void)
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printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", PROFILEHZ);
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/* Set up TIMER 2 as high speed profile clock */
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mcf_proftp = (volatile struct mcftimer *) (MCF_MBAR + MCFTIMER_BASE2);
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mcf_proftp->tmr = MCFTIMER_TMR_DISABLE;
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__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
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mcf_proftp->trr = (unsigned short) ((MCF_CLK / 16) / PROFILEHZ);
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mcf_proftp->tmr = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
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__raw_writew(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
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__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
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request_irq(mcf_profilevector, coldfire_profile_tick,
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(SA_INTERRUPT | IRQ_FLG_FAST), "profile timer", NULL);
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@ -3,7 +3,7 @@
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/*
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* mcftimer.h -- ColdFire internal TIMER support defines.
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*
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* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*/
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@ -27,6 +27,11 @@
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#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
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#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
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#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
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#elif defined(CONFIG_M532x)
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#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
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#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
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#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
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#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
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#endif
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@ -34,23 +39,14 @@
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* Define the TIMER register set addresses.
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*/
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#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
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#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
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#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
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#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
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#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
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#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
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#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
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#if defined(CONFIG_M532x)
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#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
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#else
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#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
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struct mcftimer {
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unsigned short tmr; /* Timer Mode reg (r/w) */
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unsigned short reserved1;
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unsigned short trr; /* Timer Reference (r/w) */
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unsigned short reserved2;
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unsigned short tcr; /* Timer Capture reg (r/w) */
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unsigned short reserved3;
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unsigned short tcn; /* Timer Counter reg (r/w) */
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unsigned short reserved4;
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unsigned char reserved5;
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unsigned char ter; /* Timer Event reg (r/w) */
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} __attribute__((packed));
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#endif
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/*
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* Bit definitions for the Timer Mode Register (TMR).
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