PCI: Make local functions static
Using 'make namespacecheck' identify code which should be declared static. Checked for users in other driver/archs as well. Compile tested only. This stops exporting the following interfaces to modules: pci_target_state() pci_load_saved_state() [bhelgaas: retained pci_find_next_ext_capability() and pci_cfg_space_size()] Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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e2760c54a4
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0b950f0f3c
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@ -43,7 +43,6 @@
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extern bool pciehp_poll_mode;
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extern int pciehp_poll_time;
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extern bool pciehp_debug;
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extern bool pciehp_force;
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#define dbg(format, arg...) \
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do { \
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@ -41,7 +41,7 @@
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bool pciehp_debug;
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bool pciehp_poll_mode;
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int pciehp_poll_time;
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bool pciehp_force;
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static bool pciehp_force;
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#define DRIVER_VERSION "0.4"
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#define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>"
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@ -656,6 +656,28 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
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return error;
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}
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/**
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* pci_wakeup - Wake up a PCI device
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* @pci_dev: Device to handle.
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* @ign: ignored parameter
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*/
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static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
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{
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pci_wakeup_event(pci_dev);
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pm_request_resume(&pci_dev->dev);
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return 0;
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}
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/**
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* pci_wakeup_bus - Walk given bus and wake up devices on it
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* @bus: Top bus of the subtree to walk.
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*/
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static void pci_wakeup_bus(struct pci_bus *bus)
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{
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if (bus)
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pci_walk_bus(bus, pci_wakeup, NULL);
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}
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/**
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* __pci_start_power_transition - Start power transition of a PCI device
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* @dev: PCI device to handle.
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@ -835,8 +857,8 @@ EXPORT_SYMBOL(pci_choose_state);
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#define PCI_EXP_SAVE_REGS 7
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static struct pci_cap_saved_state *pci_find_saved_cap(
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struct pci_dev *pci_dev, char cap)
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static struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *pci_dev,
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char cap)
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{
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struct pci_cap_saved_state *tmp;
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@ -1071,7 +1093,8 @@ EXPORT_SYMBOL_GPL(pci_store_saved_state);
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* @dev: PCI device that we're dealing with
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* @state: Saved state returned from pci_store_saved_state()
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*/
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int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
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static int pci_load_saved_state(struct pci_dev *dev,
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struct pci_saved_state *state)
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{
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struct pci_cap_saved_data *cap;
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@ -1099,7 +1122,6 @@ int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
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dev->state_saved = true;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_load_saved_state);
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/**
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* pci_load_and_free_saved_state - Reload the save state pointed to by state,
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@ -1531,27 +1553,6 @@ void pci_pme_wakeup_bus(struct pci_bus *bus)
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pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
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}
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/**
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* pci_wakeup - Wake up a PCI device
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* @pci_dev: Device to handle.
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* @ign: ignored parameter
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*/
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static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
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{
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pci_wakeup_event(pci_dev);
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pm_request_resume(&pci_dev->dev);
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return 0;
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}
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/**
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* pci_wakeup_bus - Walk given bus and wake up devices on it
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* @bus: Top bus of the subtree to walk.
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*/
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void pci_wakeup_bus(struct pci_bus *bus)
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{
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if (bus)
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pci_walk_bus(bus, pci_wakeup, NULL);
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}
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/**
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* pci_pme_capable - check the capability of PCI device to generate PME#
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@ -1765,7 +1766,7 @@ int pci_wake_from_d3(struct pci_dev *dev, bool enable)
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* If the platform can't manage @dev, return the deepest state from which it
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* can generate wake events, based on any available PME info.
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*/
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pci_power_t pci_target_state(struct pci_dev *dev)
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static pci_power_t pci_target_state(struct pci_dev *dev)
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{
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pci_power_t target_state = PCI_D3hot;
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@ -4206,7 +4207,6 @@ EXPORT_SYMBOL(pci_restore_state);
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EXPORT_SYMBOL(pci_pme_capable);
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EXPORT_SYMBOL(pci_pme_active);
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EXPORT_SYMBOL(pci_wake_from_d3);
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EXPORT_SYMBOL(pci_target_state);
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EXPORT_SYMBOL(pci_prepare_to_sleep);
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EXPORT_SYMBOL(pci_back_from_sleep);
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EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
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@ -6,7 +6,6 @@
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#define PCI_CFG_SPACE_SIZE 256
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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extern const unsigned char pcix_bus_speed[];
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extern const unsigned char pcie_link_speed[];
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/* Functions internal to the PCI core code */
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@ -68,7 +67,6 @@ void pci_power_up(struct pci_dev *dev);
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void pci_disable_enabled_device(struct pci_dev *dev);
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int pci_finish_runtime_suspend(struct pci_dev *dev);
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int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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void pci_wakeup_bus(struct pci_bus *bus);
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void pci_config_pm_runtime_get(struct pci_dev *dev);
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void pci_config_pm_runtime_put(struct pci_dev *dev);
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void pci_pm_init(struct pci_dev *dev);
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@ -16,7 +16,7 @@
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#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
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#define CARDBUS_RESERVE_BUSNR 3
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struct resource busn_resource = {
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static struct resource busn_resource = {
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.name = "PCI busn",
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.start = 0,
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.end = 255,
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@ -518,7 +518,7 @@ static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
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return bridge;
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}
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const unsigned char pcix_bus_speed[] = {
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static const unsigned char pcix_bus_speed[] = {
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PCI_SPEED_UNKNOWN, /* 0 */
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PCI_SPEED_66MHz_PCIX, /* 1 */
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PCI_SPEED_100MHz_PCIX, /* 2 */
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@ -999,6 +999,60 @@ void set_pcie_hotplug_bridge(struct pci_dev *pdev)
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pdev->is_hotplug_bridge = 1;
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}
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/**
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* pci_cfg_space_size - get the configuration space size of the PCI device.
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* @dev: PCI device
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*
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* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
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* have 4096 bytes. Even if the device is capable, that doesn't mean we can
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* access it. Maybe we don't have a way to generate extended config space
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* accesses, or the device is behind a reverse Express bridge. So we try
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* reading the dword at 0x100 which must either be 0 or a valid extended
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* capability header.
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*/
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static int pci_cfg_space_size_ext(struct pci_dev *dev)
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{
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u32 status;
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int pos = PCI_CFG_SPACE_SIZE;
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if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
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goto fail;
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if (status == 0xffffffff)
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goto fail;
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return PCI_CFG_SPACE_EXP_SIZE;
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fail:
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return PCI_CFG_SPACE_SIZE;
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}
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int pci_cfg_space_size(struct pci_dev *dev)
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{
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int pos;
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u32 status;
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u16 class;
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class = dev->class >> 8;
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if (class == PCI_CLASS_BRIDGE_HOST)
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return pci_cfg_space_size_ext(dev);
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if (!pci_is_pcie(dev)) {
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pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!pos)
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goto fail;
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pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
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if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
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goto fail;
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}
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return pci_cfg_space_size_ext(dev);
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fail:
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return PCI_CFG_SPACE_SIZE;
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}
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#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
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/**
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@ -1173,59 +1227,6 @@ static void pci_release_dev(struct device *dev)
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kfree(pci_dev);
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}
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/**
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* pci_cfg_space_size - get the configuration space size of the PCI device.
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* @dev: PCI device
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*
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* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
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* have 4096 bytes. Even if the device is capable, that doesn't mean we can
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* access it. Maybe we don't have a way to generate extended config space
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* accesses, or the device is behind a reverse Express bridge. So we try
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* reading the dword at 0x100 which must either be 0 or a valid extended
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* capability header.
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*/
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int pci_cfg_space_size_ext(struct pci_dev *dev)
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{
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u32 status;
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int pos = PCI_CFG_SPACE_SIZE;
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if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
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goto fail;
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if (status == 0xffffffff)
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goto fail;
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return PCI_CFG_SPACE_EXP_SIZE;
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fail:
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return PCI_CFG_SPACE_SIZE;
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}
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int pci_cfg_space_size(struct pci_dev *dev)
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{
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int pos;
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u32 status;
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u16 class;
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class = dev->class >> 8;
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if (class == PCI_CLASS_BRIDGE_HOST)
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return pci_cfg_space_size_ext(dev);
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if (!pci_is_pcie(dev)) {
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pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!pos)
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goto fail;
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pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
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if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
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goto fail;
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}
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return pci_cfg_space_size_ext(dev);
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fail:
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return PCI_CFG_SPACE_SIZE;
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}
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struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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@ -384,8 +384,6 @@ static inline int pci_channel_offline(struct pci_dev *pdev)
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return (pdev->error_state != pci_channel_io_normal);
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}
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extern struct resource busn_resource;
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struct pci_host_bridge_window {
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struct list_head list;
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struct resource *res; /* host bridge aperture (CPU address) */
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int pci_save_state(struct pci_dev *dev);
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void pci_restore_state(struct pci_dev *dev);
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struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
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int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
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int pci_load_and_free_saved_state(struct pci_dev *dev,
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struct pci_saved_state **state);
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int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
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@ -982,7 +979,6 @@ void pci_pme_active(struct pci_dev *dev, bool enable);
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int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
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bool runtime, bool enable);
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int pci_wake_from_d3(struct pci_dev *dev, bool enable);
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pci_power_t pci_target_state(struct pci_dev *dev);
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int pci_prepare_to_sleep(struct pci_dev *dev);
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int pci_back_from_sleep(struct pci_dev *dev);
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bool pci_dev_run_wake(struct pci_dev *dev);
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@ -1095,7 +1091,6 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
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void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
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void *userdata);
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int pci_cfg_space_size_ext(struct pci_dev *dev);
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int pci_cfg_space_size(struct pci_dev *dev);
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unsigned char pci_bus_max_busnr(struct pci_bus *bus);
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void pci_setup_bridge(struct pci_bus *bus);
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