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arch/tile: use a cleaner technique to enable interrupt for cpu_idle()

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Previously we used iret to atomically return to kernel PL with
interrupts enabled.  However, it turns out that we are architecturally
guaranteed that we can just set and clear the "interrupt critical
section" and only interrupt on the following instruction, so we
now do that instead, since it's cleaner.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf 2011-02-28 15:22:40 -05:00
parent a5c149c8a0
commit 0b989cac90
1 changed files with 5 additions and 11 deletions
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16
arch/tile/kernel/entry.S
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@ -91,23 +91,17 @@ STD_ENTRY(smp_nap)
/* /*
* Enable interrupts racelessly and then nap until interrupted. * Enable interrupts racelessly and then nap until interrupted.
* Architecturally, we are guaranteed that enabling interrupts via
* mtspr to INTERRUPT_CRITICAL_SECTION only interrupts at the next PC.
* This function's _cpu_idle_nap address is special; see intvec.S. * This function's _cpu_idle_nap address is special; see intvec.S.
* When interrupted at _cpu_idle_nap, we bump the PC forward 8, and * When interrupted at _cpu_idle_nap, we bump the PC forward 8, and
* as a result return to the function that called _cpu_idle(). * as a result return to the function that called _cpu_idle().
*/ */
STD_ENTRY(_cpu_idle) STD_ENTRY(_cpu_idle)
{ movei r1, 1
lnk r0 mtspr INTERRUPT_CRITICAL_SECTION, r1
movei r1, KERNEL_PL
}
{
addli r0, r0, _cpu_idle_nap - .
mtspr INTERRUPT_CRITICAL_SECTION, r1
}
IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */ IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */
mtspr SPR_EX_CONTEXT_K_1, r1 /* Kernel PL, ICS clear */ mtspr INTERRUPT_CRITICAL_SECTION, zero
mtspr SPR_EX_CONTEXT_K_0, r0
iret
.global _cpu_idle_nap .global _cpu_idle_nap
_cpu_idle_nap: _cpu_idle_nap:
nap nap