powerpc/fsl_booke: smp support for booting a relocatable kernel above 64M
When booting above the 64M for a secondary cpu, we also face the same issue as the boot cpu that the PAGE_OFFSET map two different physical address for the init tlb and the final map. So we have to use switch_to_as1/restore_to_as0 between the conversion of these two maps. When restoring to as0 for a secondary cpu, we only need to return to the caller. So add a new parameter for function restore_to_as0 for this purpose. Use LOAD_REG_ADDR_PIC to get the address of variables which may be used before we set the final map in cams for the secondary cpu. Move the setting of cams a bit earlier in order to avoid the unnecessary using of LOAD_REG_ADDR_PIC. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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@ -216,8 +216,7 @@ set_ivor:
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/* Check to see if we're the second processor, and jump
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* to the secondary_start code if so
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*/
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lis r24, boot_cpuid@h
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ori r24, r24, boot_cpuid@l
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LOAD_REG_ADDR_PIC(r24, boot_cpuid)
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lwz r24, 0(r24)
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cmpwi r24, -1
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mfspr r24,SPRN_PIR
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@ -1146,6 +1145,29 @@ _GLOBAL(__flush_disable_L1)
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/* When we get here, r24 needs to hold the CPU # */
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.globl __secondary_start
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__secondary_start:
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LOAD_REG_ADDR_PIC(r3, tlbcam_index)
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lwz r3,0(r3)
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mtctr r3
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li r26,0 /* r26 safe? */
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bl switch_to_as1
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mr r27,r3 /* tlb entry */
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/* Load each CAM entry */
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1: mr r3,r26
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bl loadcam_entry
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addi r26,r26,1
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bdnz 1b
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mr r3,r27 /* tlb entry */
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LOAD_REG_ADDR_PIC(r4, memstart_addr)
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lwz r4,0(r4)
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mr r5,r25 /* phys kernel start */
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rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
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subf r4,r5,r4 /* memstart_addr - phys kernel start */
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li r5,0 /* no device tree */
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li r6,0 /* not boot cpu */
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bl restore_to_as0
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lis r3,__secondary_hold_acknowledge@h
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ori r3,r3,__secondary_hold_acknowledge@l
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stw r24,0(r3)
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@ -1154,17 +1176,6 @@ __secondary_start:
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mr r4,r24 /* Why? */
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bl call_setup_cpu
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lis r3,tlbcam_index@ha
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lwz r3,tlbcam_index@l(r3)
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mtctr r3
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li r26,0 /* r26 safe? */
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/* Load each CAM entry */
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1: mr r3,r26
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bl loadcam_entry
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addi r26,r26,1
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bdnz 1b
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/* get current_thread_info and current */
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lis r1,secondary_ti@ha
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lwz r1,secondary_ti@l(r1)
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@ -1253,6 +1264,7 @@ _GLOBAL(switch_to_as1)
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* r3 - the tlb entry which should be invalidated
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* r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
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* r5 - device tree virtual address. If r4 is 0, r5 is ignored.
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* r6 - boot cpu
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*/
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_GLOBAL(restore_to_as0)
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mflr r0
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@ -1268,6 +1280,7 @@ _GLOBAL(restore_to_as0)
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*/
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add r9,r9,r4
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add r5,r5,r4
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add r0,r0,r4
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2: mfmsr r7
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li r8,(MSR_IS | MSR_DS)
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@ -1290,7 +1303,9 @@ _GLOBAL(restore_to_as0)
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isync
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cmpwi r4,0
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bne 3f
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cmpwi cr1,r6,0
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cror eq,4*cr1+eq,eq
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bne 3f /* offset != 0 && is_boot_cpu */
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mtlr r0
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blr
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@ -231,7 +231,7 @@ void __init adjust_total_lowmem(void)
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i = switch_to_as1();
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__max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);
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restore_to_as0(i, 0, 0);
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restore_to_as0(i, 0, 0, 1);
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pr_info("Memory CAM mapping: ");
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for (i = 0; i < tlbcam_index - 1; i++)
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@ -302,7 +302,7 @@ notrace void __init relocate_init(u64 dt_ptr, phys_addr_t start)
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else
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map_mem_in_cams_addr(start, PAGE_OFFSET + offset,
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0x4000000, CONFIG_LOWMEM_CAM_NUM);
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restore_to_as0(n, offset, __va(dt_ptr));
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restore_to_as0(n, offset, __va(dt_ptr), 1);
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/* We should never reach here */
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panic("Relocation error");
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}
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@ -149,7 +149,7 @@ extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(unsigned long top);
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extern void adjust_total_lowmem(void);
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extern int switch_to_as1(void);
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extern void restore_to_as0(int esel, int offset, void *dt_ptr);
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extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
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#endif
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extern void loadcam_entry(unsigned int index);
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@ -402,7 +402,9 @@ _GLOBAL(set_context)
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* Load TLBCAM[index] entry in to the L2 CAM MMU
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*/
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_GLOBAL(loadcam_entry)
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LOAD_REG_ADDR(r4, TLBCAM)
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mflr r5
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LOAD_REG_ADDR_PIC(r4, TLBCAM)
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mtlr r5
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mulli r5,r3,TLBCAM_SIZE
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add r3,r5,r4
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lwz r4,TLBCAM_MAS0(r3)
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