genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as a write is a good model for an edge (you can't "unwrite" something). On the other hand, routing zillions of wires in an SoC because you need level interrupts is a bit extreme. People have come up with a variety of schemes to support this, which involves sending two messages: one to signal the interrupt, and one to clear it. Since the kernel cannot represent this, we've ended up with side-band mechanisms that are pretty awful. Instead, let's acknoledge the requirement, and ensure that, under the right circumstances, the irq_compose_msg and irq_write_msg can take as a parameter an array of two messages instead of a pointer to a single one. We also add some checking that the compose method only clobbers the second message if the MSI domain has been created with the MSI_FLAG_LEVEL_CAPABLE flags. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <robh@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
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@ -289,6 +289,8 @@ enum {
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* MSI_FLAG_ACTIVATE_EARLY has been set.
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*/
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MSI_FLAG_MUST_REACTIVATE = (1 << 5),
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/* Is level-triggered capable, using two messages */
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MSI_FLAG_LEVEL_CAPABLE = (1 << 6),
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};
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int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask,
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@ -76,6 +76,19 @@ static inline void irq_chip_write_msi_msg(struct irq_data *data,
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data->chip->irq_write_msi_msg(data, msg);
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}
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static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
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{
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struct msi_domain_info *info = domain->host_data;
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/*
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* If the MSI provider has messed with the second message and
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* not advertized that it is level-capable, signal the breakage.
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*/
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WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
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(info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
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(msg[1].address_lo || msg[1].address_hi || msg[1].data));
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}
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/**
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* msi_domain_set_affinity - Generic affinity setter function for MSI domains
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* @irq_data: The irq data associated to the interrupt
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@ -89,13 +102,14 @@ int msi_domain_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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struct irq_data *parent = irq_data->parent_data;
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struct msi_msg msg;
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struct msi_msg msg[2] = { [1] = { }, };
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
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BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
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irq_chip_write_msi_msg(irq_data, &msg);
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BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
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msi_check_level(irq_data->domain, msg);
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irq_chip_write_msi_msg(irq_data, msg);
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}
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return ret;
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@ -104,20 +118,21 @@ int msi_domain_set_affinity(struct irq_data *irq_data,
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static int msi_domain_activate(struct irq_domain *domain,
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struct irq_data *irq_data, bool early)
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{
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struct msi_msg msg;
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struct msi_msg msg[2] = { [1] = { }, };
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BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
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irq_chip_write_msi_msg(irq_data, &msg);
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BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
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msi_check_level(irq_data->domain, msg);
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irq_chip_write_msi_msg(irq_data, msg);
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return 0;
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}
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static void msi_domain_deactivate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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struct msi_msg msg;
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struct msi_msg msg[2];
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memset(&msg, 0, sizeof(msg));
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irq_chip_write_msi_msg(irq_data, &msg);
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memset(msg, 0, sizeof(msg));
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irq_chip_write_msi_msg(irq_data, msg);
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}
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static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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