[PATCH] atyfb: VT/GT cleanup
Clean up VT and GT chip descriptions. All B revision VT chips are called 264VT3. Verified from pictures of the chips as the specs are a bit unlear in this. GT revision B1 is Rage II, B2 is Rage II+. Specs and chip pictures seem to agree. VT revision A4 is 264VT2. Revision A3 is probably a plain 264VT. Signed-off-by: Ville Syrjälä <syrjala@sci.fi> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -380,11 +380,12 @@ static struct {
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#ifdef CONFIG_FB_ATY_CT
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{ PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
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{ PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
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{ PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
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{ PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
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{ PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
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/* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
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{ PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, 100, ATI_CHIP_264GTB },
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{ PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
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{ PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
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{ PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
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{ PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
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/* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
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@ -460,44 +461,63 @@ static int __devinit correct_chipset(struct atyfb_par *par)
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#endif
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#ifdef CONFIG_FB_ATY_CT
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case PCI_CHIP_MACH64VT:
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rev &= 0xc7;
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if(rev == 0x00) {
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name = "ATI264VTA3 (Mach64 VT)";
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par->pll_limits.pll_max = 170;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264VT;
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} else if(rev == 0x40) {
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name = "ATI264VTA4 (Mach64 VT)";
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par->pll_limits.pll_max = 200;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
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} else {
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name = "ATI264VTB (Mach64 VT)";
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switch (rev & 0x07) {
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case 0x00:
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switch (rev & 0xc0) {
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case 0x00:
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name = "ATI264VT (A3) (Mach64 VT)";
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par->pll_limits.pll_max = 170;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264VT;
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break;
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case 0x40:
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name = "ATI264VT2 (A4) (Mach64 VT)";
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par->pll_limits.pll_max = 200;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
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break;
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}
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break;
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case 0x01:
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name = "ATI264VT3 (B1) (Mach64 VT)";
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par->pll_limits.pll_max = 200;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264VTB;
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break;
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case 0x02:
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name = "ATI264VT3 (B2) (Mach64 VT)";
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par->pll_limits.pll_max = 200;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264VT3;
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break;
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}
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break;
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case PCI_CHIP_MACH64GT:
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rev &= 0x07;
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if(rev == 0x01) {
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switch (rev & 0x07) {
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case 0x01:
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name = "3D RAGE II (Mach64 GT)";
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par->pll_limits.pll_max = 170;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 80;
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par->features = ATI_CHIP_264GTB;
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} else if(rev == 0x02) {
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break;
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case 0x02:
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name = "3D RAGE II+ (Mach64 GT)";
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par->pll_limits.pll_max = 200;
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par->pll_limits.mclk = 67;
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par->pll_limits.xclk = 67;
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par->pll_limits.ecp_max = 100;
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par->features = ATI_CHIP_264GTB;
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break;
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}
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break;
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#endif
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