qlcnic: Fix a bug in setting up NIC partitioning mode
The driver was not detecting the presence of NIC partitioning capability of the firmware properly. Now, it checks the eswitch set bit in the FW capabilities register and accordingly sets the driver mode as NPAR capable or not. Signed-off-by: Anirban Chakraborty <anirban.chakraborty@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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8c76368174
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0e33c6649e
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@ -891,7 +891,7 @@ struct qlcnic_mac_req {
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#define QLCNIC_LRO_ENABLED 0x08
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#define QLCNIC_BRIDGE_ENABLED 0X10
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#define QLCNIC_DIAG_ENABLED 0x20
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#define QLCNIC_NPAR_ENABLED 0x40
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#define QLCNIC_ESWITCH_ENABLED 0x40
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#define QLCNIC_IS_MSI_FAMILY(adapter) \
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((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
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@ -637,6 +637,11 @@ int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, u8 func_id)
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adapter->capabilities = le32_to_cpu(nic_info->capabilities);
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adapter->max_mac_filters = nic_info->max_mac_filters;
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if (adapter->capabilities & BIT_6)
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adapter->flags |= QLCNIC_ESWITCH_ENABLED;
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else
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adapter->flags &= ~QLCNIC_ESWITCH_ENABLED;
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dev_info(&adapter->pdev->dev,
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"phy port: %d switch_mode: %d,\n"
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"\tmax_tx_q: %d max_rx_q: %d min_tx_bw: 0x%x,\n"
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@ -502,39 +502,28 @@ qlcnic_set_function_modes(struct qlcnic_adapter *adapter)
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if (QLC_DEV_CLR_REF_CNT(ref_count, adapter->ahw.pci_func))
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goto err_npar;
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for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
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id = adapter->npars[i].id;
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if (adapter->npars[i].type != QLCNIC_TYPE_NIC ||
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id == adapter->ahw.pci_func)
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continue;
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data |= (qlcnic_config_npars & QLC_DEV_SET_DRV(0xf, id));
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if (qlcnic_config_npars) {
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for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
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id = adapter->npars[i].id;
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if (adapter->npars[i].type != QLCNIC_TYPE_NIC ||
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id == adapter->ahw.pci_func)
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continue;
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data |= (qlcnic_config_npars &
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QLC_DEV_SET_DRV(0xf, id));
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}
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} else {
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data = readl(priv_op);
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data = (data & ~QLC_DEV_SET_DRV(0xf, adapter->ahw.pci_func)) |
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(QLC_DEV_SET_DRV(QLCNIC_MGMT_FUNC,
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adapter->ahw.pci_func));
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}
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writel(data, priv_op);
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err_npar:
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qlcnic_api_unlock(adapter);
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err_lock:
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return ret;
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}
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static u8
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qlcnic_set_mgmt_driver(struct qlcnic_adapter *adapter)
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{
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u8 i, ret = 0;
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if (qlcnic_get_pci_info(adapter))
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return ret;
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/* Set the eswitch */
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for (i = 0; i < QLCNIC_NIU_MAX_XG_PORTS; i++) {
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if (!qlcnic_get_eswitch_capabilities(adapter, i,
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&adapter->eswitch[i])) {
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ret++;
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qlcnic_toggle_eswitch(adapter, i, ret);
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}
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}
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return ret;
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}
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static u32
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qlcnic_get_driver_mode(struct qlcnic_adapter *adapter)
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{
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@ -550,6 +539,7 @@ qlcnic_get_driver_mode(struct qlcnic_adapter *adapter)
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adapter->nic_ops = &qlcnic_ops;
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adapter->fw_hal_version = QLCNIC_FW_BASE;
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adapter->ahw.pci_func = PCI_FUNC(adapter->pdev->devfn);
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adapter->capabilities = QLCRD32(adapter, CRB_FW_CAPABILITIES_1);
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dev_info(&adapter->pdev->dev,
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"FW does not support nic partion\n");
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return adapter->fw_hal_version;
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@ -562,29 +552,28 @@ qlcnic_get_driver_mode(struct qlcnic_adapter *adapter)
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func = (func - msix_base)/QLCNIC_MSIX_TBL_PGSIZE;
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adapter->ahw.pci_func = func;
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qlcnic_get_nic_info(adapter, adapter->ahw.pci_func);
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if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
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adapter->nic_ops = &qlcnic_ops;
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return adapter->fw_hal_version;
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}
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/* Determine function privilege level */
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priv_op = adapter->ahw.pci_base0 + QLCNIC_DRV_OP_MODE;
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op_mode = readl(priv_op);
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if (op_mode == QLC_DEV_DRV_DEFAULT) {
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if (op_mode == QLC_DEV_DRV_DEFAULT)
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priv_level = QLCNIC_MGMT_FUNC;
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if (qlcnic_api_lock(adapter))
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return 0;
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op_mode = (op_mode & ~QLC_DEV_SET_DRV(0xf, func)) |
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(QLC_DEV_SET_DRV(QLCNIC_MGMT_FUNC, func));
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writel(op_mode, priv_op);
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qlcnic_api_unlock(adapter);
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} else
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else
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priv_level = QLC_DEV_GET_DRV(op_mode, adapter->ahw.pci_func);
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switch (priv_level) {
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case QLCNIC_MGMT_FUNC:
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adapter->op_mode = QLCNIC_MGMT_FUNC;
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adapter->nic_ops = &qlcnic_pf_ops;
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qlcnic_get_pci_info(adapter);
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/* Set privilege level for other functions */
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if (qlcnic_config_npars)
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qlcnic_set_function_modes(adapter);
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qlcnic_dev_set_npar_ready(adapter);
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qlcnic_set_function_modes(adapter);
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dev_info(&adapter->pdev->dev,
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"HAL Version: %d, Management function\n",
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adapter->fw_hal_version);
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@ -716,11 +705,6 @@ qlcnic_check_options(struct qlcnic_adapter *adapter)
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dev_info(&pdev->dev, "firmware v%d.%d.%d\n",
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fw_major, fw_minor, fw_build);
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if (adapter->fw_hal_version == QLCNIC_FW_NPAR)
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qlcnic_get_nic_info(adapter, adapter->ahw.pci_func);
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else
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adapter->capabilities = QLCRD32(adapter, CRB_FW_CAPABILITIES_1);
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adapter->flags &= ~QLCNIC_LRO_ENABLED;
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if (adapter->ahw.port_type == QLCNIC_XGBE) {
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@ -731,6 +715,8 @@ qlcnic_check_options(struct qlcnic_adapter *adapter)
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adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
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}
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qlcnic_get_nic_info(adapter, adapter->ahw.pci_func);
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adapter->msix_supported = !!use_msi_x;
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adapter->rss_supported = !!use_msi_x;
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@ -797,13 +783,11 @@ wait_init:
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QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_READY);
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qlcnic_idc_debug_info(adapter, 1);
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qlcnic_dev_set_npar_ready(adapter);
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qlcnic_check_options(adapter);
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if (adapter->fw_hal_version != QLCNIC_FW_BASE &&
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adapter->op_mode == QLCNIC_MGMT_FUNC)
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qlcnic_set_mgmt_driver(adapter);
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if (adapter->flags & QLCNIC_ESWITCH_ENABLED &&
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adapter->op_mode != QLCNIC_NON_PRIV_FUNC)
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qlcnic_dev_set_npar_ready(adapter);
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adapter->need_fw_reset = 0;
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@ -2449,10 +2433,6 @@ qlcnic_dev_set_npar_ready(struct qlcnic_adapter *adapter)
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{
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u32 state;
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if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC ||
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adapter->fw_hal_version == QLCNIC_FW_BASE)
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return;
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if (qlcnic_api_lock(adapter))
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return;
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