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MLK-16461-2 ARM64: dts: fsl-imx8mq.dtsi: set property fsl,strobe-dll-delay-target 

On some i.MX8MQ-EVK A0/A1 board, we may meet eMMC read data CRC error in
HS400 mode. This is because the delay cell set for the strobe pad
is not correct. Before this patch, usdhc driver default set this delay
cell to value 7, but for some board, only value 3~6 can pass read
operation in HS400 mode, some board, the pass value is 2~10, and
some board, the pass value is 3~8. So the default value 7 can't
make sure all the board can pass eMMC read in HS400.

This patch set the value 5 to fsl,strobe-dll-delay-target, make sure
all the board can work stable in HS400 mode.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
pull/10/head
Haibo Chen 2017-09-15 20:07:22 +08:00 committed by Jason Liu
parent 3dfc1e9647
commit 0e8ac60237
1 changed files with 3 additions and 2 deletions
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5
arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
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@ -722,7 +722,8 @@
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
fsl,strobe-dll-delay-target = <5>;
bus-width = <4>;
status = "disabled";
};
@ -736,7 +737,7 @@
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};