openrisc: add atomic bitops
This utilize the load-link/store-conditional l.lwa and l.swa instructions to implement the atomic bitops. When those instructions are not available emulation is provided. Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by Alan Cox https://lkml.org/lkml/2014/7/23/666, implement test_and_change_bit] Signed-off-by: Stafford Horne <shorne@gmail.com>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/atomic.h>
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#include <asm/bitops/atomic.h>
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#include <asm-generic/bitops/non-atomic.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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123
arch/openrisc/include/asm/bitops/atomic.h
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123
arch/openrisc/include/asm/bitops/atomic.h
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/*
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* Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_OPENRISC_BITOPS_ATOMIC_H
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#define __ASM_OPENRISC_BITOPS_ATOMIC_H
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static inline void set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long tmp;
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__asm__ __volatile__(
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"1: l.lwa %0,0(%1) \n"
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" l.or %0,%0,%2 \n"
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" l.swa 0(%1),%0 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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: "=&r"(tmp)
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: "r"(p), "r"(mask)
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: "cc", "memory");
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}
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long tmp;
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__asm__ __volatile__(
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"1: l.lwa %0,0(%1) \n"
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" l.and %0,%0,%2 \n"
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" l.swa 0(%1),%0 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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: "=&r"(tmp)
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: "r"(p), "r"(~mask)
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: "cc", "memory");
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}
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static inline void change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long tmp;
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__asm__ __volatile__(
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"1: l.lwa %0,0(%1) \n"
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" l.xor %0,%0,%2 \n"
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" l.swa 0(%1),%0 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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: "=&r"(tmp)
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: "r"(p), "r"(mask)
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: "cc", "memory");
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}
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long tmp;
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__asm__ __volatile__(
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"1: l.lwa %0,0(%2) \n"
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" l.or %1,%0,%3 \n"
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" l.swa 0(%2),%1 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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: "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(mask)
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: "cc", "memory");
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return (old & mask) != 0;
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}
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long tmp;
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__asm__ __volatile__(
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"1: l.lwa %0,0(%2) \n"
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" l.and %1,%0,%3 \n"
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" l.swa 0(%2),%1 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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: "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(~mask)
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: "cc", "memory");
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return (old & mask) != 0;
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}
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long tmp;
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__asm__ __volatile__(
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"1: l.lwa %0,0(%2) \n"
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" l.xor %1,%0,%3 \n"
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" l.swa 0(%2),%1 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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: "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(mask)
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: "cc", "memory");
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return (old & mask) != 0;
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}
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#endif /* __ASM_OPENRISC_BITOPS_ATOMIC_H */
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