Merge branch 'timers-clocksource-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'timers-clocksource-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: clocksource: convert mips to generic i8253 clocksource clocksource: convert x86 to generic i8253 clocksource clocksource: convert footbridge to generic i8253 clocksource clocksource: add common i8253 PIT clocksource blackfin: convert to clocksource_register_hz mips: convert to clocksource_register_hz/khz sparc: convert to clocksource_register_hz/khz alpha: convert to clocksource_register_hz microblaze: convert to clocksource_register_hz/khz ia64: convert to clocksource_register_hz/khz x86: Convert remaining x86 clocksources to clocksource_register_hz/khz Make clocksource name const
This commit is contained in:
commit
0f1bdc1815
15
arch/arm/include/asm/i8253.h
Normal file
15
arch/arm/include/asm/i8253.h
Normal file
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@ -0,0 +1,15 @@
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#ifndef __ASMARM_I8253_H
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#define __ASMARM_I8253_H
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/* i8253A PIT registers */
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#define PIT_MODE 0x43
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#define PIT_CH0 0x40
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#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ)
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extern raw_spinlock_t i8253_lock;
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#define outb_pit outb_p
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#define inb_pit inb_p
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#endif
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@ -4,6 +4,7 @@ menu "Footbridge Implementations"
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config ARCH_CATS
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bool "CATS"
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select CLKSRC_I8253
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select FOOTBRIDGE_HOST
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select ISA
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select ISA_DMA
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@ -59,6 +60,7 @@ config ARCH_EBSA285_HOST
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config ARCH_NETWINDER
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bool "NetWinder"
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select CLKSRC_I8253
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select FOOTBRIDGE_HOST
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select ISA
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select ISA_DMA
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@ -10,53 +10,16 @@
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/timex.h>
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#include <asm/irq.h>
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#include <asm/i8253.h>
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#include <asm/mach/time.h>
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#include "common.h"
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#define PIT_MODE 0x43
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#define PIT_CH0 0x40
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#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ)
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static cycle_t pit_read(struct clocksource *cs)
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{
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unsigned long flags;
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static int old_count;
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static u32 old_jifs;
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int count;
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u32 jifs;
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raw_local_irq_save(flags);
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jifs = jiffies;
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outb_p(0x00, PIT_MODE); /* latch the count */
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count = inb_p(PIT_CH0); /* read the latched count */
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count |= inb_p(PIT_CH0) << 8;
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if (count > old_count && jifs == old_jifs)
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count = old_count;
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old_count = count;
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old_jifs = jifs;
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raw_local_irq_restore(flags);
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count = (PIT_LATCH - 1) - count;
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return (cycle_t)(jifs * PIT_LATCH) + count;
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}
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static struct clocksource pit_cs = {
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.name = "pit",
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.rating = 110,
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.read = pit_read,
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.mask = CLOCKSOURCE_MASK(32),
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};
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DEFINE_RAW_SPINLOCK(i8253_lock);
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static void pit_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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@ -121,7 +84,7 @@ static void __init isa_timer_init(void)
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pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce);
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pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce);
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clocksource_register_hz(&pit_cs, PIT_TICK_RATE);
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clocksource_i8253_init();
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setup_irq(pit_ce.irq, &pit_timer_irq);
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clockevents_register_device(&pit_ce);
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@ -23,29 +23,6 @@
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#include <asm/gptimers.h>
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#include <asm/nmi.h>
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/* Accelerators for sched_clock()
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* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george@mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz) / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift.
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*
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* We can use khz divisor instead of mhz to keep a better precision, since
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* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
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* (mathieu.desnoyers@polymtl.ca)
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*
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* -johnstul@us.ibm.com "math is hard, lets go shopping!"
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*/
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#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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@ -63,7 +40,6 @@ static struct clocksource bfin_cs_cycles = {
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.rating = 400,
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.read = bfin_read_cycles,
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.mask = CLOCKSOURCE_MASK(64),
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.shift = CYC2NS_SCALE_FACTOR,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -75,10 +51,7 @@ static inline unsigned long long bfin_cs_cycles_sched_clock(void)
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static int __init bfin_cs_cycles_init(void)
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{
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bfin_cs_cycles.mult = \
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clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
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if (clocksource_register(&bfin_cs_cycles))
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if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
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panic("failed to register clocksource");
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return 0;
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@ -111,7 +84,6 @@ static struct clocksource bfin_cs_gptimer0 = {
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.rating = 350,
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.read = bfin_read_gptimer0,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = CYC2NS_SCALE_FACTOR,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -125,10 +97,7 @@ static int __init bfin_cs_gptimer0_init(void)
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{
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setup_gptimer0();
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bfin_cs_gptimer0.mult = \
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clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
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if (clocksource_register(&bfin_cs_gptimer0))
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if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
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panic("failed to register clocksource");
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return 0;
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@ -31,8 +31,6 @@ static struct clocksource clocksource_cyclone = {
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.rating = 300,
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.read = read_cyclone,
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.mask = (1LL << 40) - 1,
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.mult = 0, /*to be calculated*/
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -118,9 +116,7 @@ int __init init_cyclone_clock(void)
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/* initialize last tick */
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cyclone_mc = cyclone_timer;
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clocksource_cyclone.fsys_mmio = cyclone_timer;
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clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
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clocksource_cyclone.shift);
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clocksource_register(&clocksource_cyclone);
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clocksource_register_hz(&clocksource_cyclone, CYCLONE_TIMER_FREQ);
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return 0;
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}
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@ -73,8 +73,6 @@ static struct clocksource clocksource_itc = {
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.rating = 350,
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.read = itc_get_cycles,
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.mask = CLOCKSOURCE_MASK(64),
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.mult = 0, /*to be calculated*/
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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#ifdef CONFIG_PARAVIRT
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.resume = paravirt_clocksource_resume,
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@ -365,11 +363,8 @@ ia64_init_itm (void)
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ia64_cpu_local_tick();
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if (!itc_clocksource) {
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/* Sort out mult/shift values: */
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clocksource_itc.mult =
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clocksource_hz2mult(local_cpu_data->itc_freq,
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clocksource_itc.shift);
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clocksource_register(&clocksource_itc);
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clocksource_register_hz(&clocksource_itc,
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local_cpu_data->itc_freq);
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itc_clocksource = &clocksource_itc;
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}
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}
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@ -33,8 +33,6 @@ static struct clocksource clocksource_sn2 = {
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.rating = 450,
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.read = read_sn2,
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.mask = (1LL << 55) - 1,
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.mult = 0,
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -57,9 +55,7 @@ ia64_sn_udelay (unsigned long usecs)
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void __init sn_timer_init(void)
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{
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clocksource_sn2.fsys_mmio = RTC_COUNTER_ADDR;
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clocksource_sn2.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
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clocksource_sn2.shift);
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clocksource_register(&clocksource_sn2);
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clocksource_register_hz(&clocksource_sn2, sn_rtc_cycles_per_second);
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ia64_udelay = &ia64_sn_udelay;
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}
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@ -217,16 +217,12 @@ static struct clocksource clocksource_microblaze = {
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.rating = 300,
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.read = microblaze_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 8, /* I can shift it */
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init microblaze_clocksource_init(void)
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{
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clocksource_microblaze.mult =
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clocksource_hz2mult(timer_clock_freq,
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clocksource_microblaze.shift);
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if (clocksource_register(&clocksource_microblaze))
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if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
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panic("failed to register clocksource");
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/* stop timer1 */
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@ -2395,6 +2395,7 @@ config MMU
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config I8253
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bool
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select CLKSRC_I8253
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select MIPS_EXTERNAL_TIMER
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config ZONE_DMA32
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|
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@ -141,8 +141,7 @@ static int __init alchemy_time_init(unsigned int m2int)
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goto cntr_err;
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/* register counter1 clocksource and event device */
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clocksource_set_clock(&au1x_counter1_clocksource, 32768);
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clocksource_register(&au1x_counter1_clocksource);
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clocksource_register_hz(&au1x_counter1_clocksource, 32768);
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cd->shift = 32;
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cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
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|
|
|
@ -105,8 +105,7 @@ unsigned long long notrace sched_clock(void)
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void __init plat_time_init(void)
|
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{
|
||||
clocksource_mips.rating = 300;
|
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clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
|
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clocksource_register(&clocksource_mips);
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clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
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}
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static u64 octeon_udelay_factor;
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|
|
|
@ -12,8 +12,13 @@
|
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#define PIT_CH0 0x40
|
||||
#define PIT_CH2 0x42
|
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|
||||
#define PIT_LATCH LATCH
|
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|
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extern raw_spinlock_t i8253_lock;
|
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|
||||
extern void setup_pit_timer(void);
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|
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#define inb_pit inb_p
|
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#define outb_pit outb_p
|
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|
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#endif /* __ASM_I8253_H */
|
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|
|
|
@ -84,12 +84,6 @@ static inline int init_mips_clocksource(void)
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|||
#endif
|
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}
|
||||
|
||||
static inline void clocksource_set_clock(struct clocksource *cs,
|
||||
unsigned int clock)
|
||||
{
|
||||
clocksource_calc_mult_shift(cs, clock, 4);
|
||||
}
|
||||
|
||||
static inline void clockevent_set_clock(struct clock_event_device *cd,
|
||||
unsigned int clock)
|
||||
{
|
||||
|
|
|
@ -121,8 +121,7 @@ void __init plat_time_init(void)
|
|||
|
||||
clockevents_register_device(&jz4740_clockevent);
|
||||
|
||||
clocksource_set_clock(&jz4740_clocksource, clk_rate);
|
||||
ret = clocksource_register(&jz4740_clocksource);
|
||||
ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
|
||||
|
||||
if (ret)
|
||||
printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
|
||||
|
|
|
@ -51,8 +51,7 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
|
|||
{
|
||||
struct txx9_tmr_reg __iomem *tmrptr;
|
||||
|
||||
clocksource_set_clock(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
|
||||
clocksource_register(&txx9_clocksource.cs);
|
||||
clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
|
||||
|
||||
tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
|
||||
__raw_writel(TCR_BASE, &tmrptr->tcr);
|
||||
|
|
|
@ -49,6 +49,5 @@ void __init sb1480_clocksource_init(void)
|
|||
|
||||
plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
|
||||
zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
|
||||
clocksource_set_clock(cs, zbbus);
|
||||
clocksource_register(cs);
|
||||
clocksource_register_hz(cs, zbbus);
|
||||
}
|
||||
|
|
|
@ -59,7 +59,5 @@ void __init dec_ioasic_clocksource_init(void)
|
|||
printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
|
||||
|
||||
clocksource_dec.rating = 200 + freq / 10000000;
|
||||
clocksource_set_clock(&clocksource_dec, freq);
|
||||
|
||||
clocksource_register(&clocksource_dec);
|
||||
clocksource_register_hz(&clocksource_dec, freq);
|
||||
}
|
||||
|
|
|
@ -78,9 +78,7 @@ static void __init powertv_c0_hpt_clocksource_init(void)
|
|||
|
||||
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
|
||||
|
||||
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
|
||||
|
||||
clocksource_register(&clocksource_mips);
|
||||
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -130,43 +128,16 @@ static struct clocksource clocksource_tim_c = {
|
|||
/**
|
||||
* powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
|
||||
*
|
||||
* The hard part here is coming up with a constant k and shift s such that
|
||||
* the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
|
||||
* when shifted right by s, yields the corresponding number of nanoseconds.
|
||||
* We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
|
||||
* 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
|
||||
* number of nanoseconds. Since the TIM_C value has 48 bits and the math is
|
||||
* done in 64 bits, avoiding an overflow means that k must be less than
|
||||
* 64 - 48 = 16 bits.
|
||||
* 1 / (27,000,000/8) seconds.
|
||||
*/
|
||||
static void __init powertv_tim_c_clocksource_init(void)
|
||||
{
|
||||
int prescale;
|
||||
unsigned long dividend;
|
||||
unsigned long k;
|
||||
int s;
|
||||
const int max_k_bits = (64 - 48) - 1;
|
||||
const unsigned long billion = 1000000000;
|
||||
const unsigned long counts_per_second = 27000000 / 8;
|
||||
|
||||
prescale = BITS_PER_LONG - ilog2(billion) - 1;
|
||||
dividend = billion << prescale;
|
||||
k = dividend / counts_per_second;
|
||||
s = ilog2(k) - max_k_bits;
|
||||
|
||||
if (s < 0)
|
||||
s = prescale;
|
||||
|
||||
else {
|
||||
k >>= s;
|
||||
s += prescale;
|
||||
}
|
||||
|
||||
clocksource_tim_c.mult = k;
|
||||
clocksource_tim_c.shift = s;
|
||||
clocksource_tim_c.rating = 200;
|
||||
|
||||
clocksource_register(&clocksource_tim_c);
|
||||
clocksource_register_hz(&clocksource_tim_c, counts_per_second);
|
||||
tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
|
||||
}
|
||||
|
||||
|
|
|
@ -30,9 +30,7 @@ int __init init_r4k_clocksource(void)
|
|||
/* Calculate a somewhat reasonable rating value */
|
||||
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
|
||||
|
||||
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
|
||||
|
||||
clocksource_register(&clocksource_mips);
|
||||
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -65,6 +65,5 @@ void __init sb1250_clocksource_init(void)
|
|||
IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
|
||||
R_SCD_TIMER_CFG)));
|
||||
|
||||
clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
|
||||
clocksource_register(cs);
|
||||
clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
|
||||
}
|
||||
|
|
|
@ -125,87 +125,11 @@ void __init setup_pit_timer(void)
|
|||
setup_irq(0, &irq0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Since the PIT overflows every tick, its not very useful
|
||||
* to just read by itself. So use jiffies to emulate a free
|
||||
* running counter:
|
||||
*/
|
||||
static cycle_t pit_read(struct clocksource *cs)
|
||||
{
|
||||
unsigned long flags;
|
||||
int count;
|
||||
u32 jifs;
|
||||
static int old_count;
|
||||
static u32 old_jifs;
|
||||
|
||||
raw_spin_lock_irqsave(&i8253_lock, flags);
|
||||
/*
|
||||
* Although our caller may have the read side of xtime_lock,
|
||||
* this is now a seqlock, and we are cheating in this routine
|
||||
* by having side effects on state that we cannot undo if
|
||||
* there is a collision on the seqlock and our caller has to
|
||||
* retry. (Namely, old_jifs and old_count.) So we must treat
|
||||
* jiffies as volatile despite the lock. We read jiffies
|
||||
* before latching the timer count to guarantee that although
|
||||
* the jiffies value might be older than the count (that is,
|
||||
* the counter may underflow between the last point where
|
||||
* jiffies was incremented and the point where we latch the
|
||||
* count), it cannot be newer.
|
||||
*/
|
||||
jifs = jiffies;
|
||||
outb_p(0x00, PIT_MODE); /* latch the count ASAP */
|
||||
count = inb_p(PIT_CH0); /* read the latched count */
|
||||
count |= inb_p(PIT_CH0) << 8;
|
||||
|
||||
/* VIA686a test code... reset the latch if count > max + 1 */
|
||||
if (count > LATCH) {
|
||||
outb_p(0x34, PIT_MODE);
|
||||
outb_p(LATCH & 0xff, PIT_CH0);
|
||||
outb(LATCH >> 8, PIT_CH0);
|
||||
count = LATCH - 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* It's possible for count to appear to go the wrong way for a
|
||||
* couple of reasons:
|
||||
*
|
||||
* 1. The timer counter underflows, but we haven't handled the
|
||||
* resulting interrupt and incremented jiffies yet.
|
||||
* 2. Hardware problem with the timer, not giving us continuous time,
|
||||
* the counter does small "jumps" upwards on some Pentium systems,
|
||||
* (see c't 95/10 page 335 for Neptun bug.)
|
||||
*
|
||||
* Previous attempts to handle these cases intelligently were
|
||||
* buggy, so we just do the simple thing now.
|
||||
*/
|
||||
if (count > old_count && jifs == old_jifs) {
|
||||
count = old_count;
|
||||
}
|
||||
old_count = count;
|
||||
old_jifs = jifs;
|
||||
|
||||
raw_spin_unlock_irqrestore(&i8253_lock, flags);
|
||||
|
||||
count = (LATCH - 1) - count;
|
||||
|
||||
return (cycle_t)(jifs * LATCH) + count;
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_pit = {
|
||||
.name = "pit",
|
||||
.rating = 110,
|
||||
.read = pit_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.mult = 0,
|
||||
.shift = 20,
|
||||
};
|
||||
|
||||
static int __init init_pit_clocksource(void)
|
||||
{
|
||||
if (num_possible_cpus() > 1) /* PIT does not scale! */
|
||||
return 0;
|
||||
|
||||
clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
|
||||
return clocksource_register(&clocksource_pit);
|
||||
return clocksource_i8253_init();
|
||||
}
|
||||
arch_initcall(init_pit_clocksource);
|
||||
|
|
|
@ -201,8 +201,6 @@ static struct clocksource clocksource_mfgpt = {
|
|||
.rating = 120, /* Functional for real use, but not desired */
|
||||
.read = mfgpt_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.mult = 0,
|
||||
.shift = 22,
|
||||
};
|
||||
|
||||
int __init init_mfgpt_clocksource(void)
|
||||
|
@ -210,8 +208,7 @@ int __init init_mfgpt_clocksource(void)
|
|||
if (num_possible_cpus() > 1) /* MFGPT does not scale! */
|
||||
return 0;
|
||||
|
||||
clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
|
||||
return clocksource_register(&clocksource_mfgpt);
|
||||
return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
|
||||
}
|
||||
|
||||
arch_initcall(init_mfgpt_clocksource);
|
||||
|
|
|
@ -163,8 +163,7 @@ static void __init hub_rt_clocksource_init(void)
|
|||
{
|
||||
struct clocksource *cs = &hub_rt_clocksource;
|
||||
|
||||
clocksource_set_clock(cs, CYCLES_PER_SEC);
|
||||
clocksource_register(cs);
|
||||
clocksource_register_hz(cs, CYCLES_PER_SEC);
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
|
|
|
@ -8,6 +8,7 @@ config 64BIT
|
|||
|
||||
config X86_32
|
||||
def_bool !64BIT
|
||||
select CLKSRC_I8253
|
||||
|
||||
config X86_64
|
||||
def_bool 64BIT
|
||||
|
|
|
@ -6,6 +6,8 @@
|
|||
#define PIT_CH0 0x40
|
||||
#define PIT_CH2 0x42
|
||||
|
||||
#define PIT_LATCH LATCH
|
||||
|
||||
extern raw_spinlock_t i8253_lock;
|
||||
|
||||
extern struct clock_event_device *global_clock_event;
|
||||
|
|
|
@ -177,7 +177,6 @@ static struct clocksource clocksource_apbt = {
|
|||
.rating = APBT_CLOCKSOURCE_RATING,
|
||||
.read = apbt_read_clocksource,
|
||||
.mask = APBT_MASK,
|
||||
.shift = APBT_SHIFT,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
.resume = apbt_restart_clocksource,
|
||||
};
|
||||
|
@ -543,14 +542,7 @@ static int apbt_clocksource_register(void)
|
|||
if (t1 == apbt_read_clocksource(&clocksource_apbt))
|
||||
panic("APBT counter not counting. APBT disabled\n");
|
||||
|
||||
/*
|
||||
* initialize and register APBT clocksource
|
||||
* convert that to ns/clock cycle
|
||||
* mult = (ns/c) * 2^APBT_SHIFT
|
||||
*/
|
||||
clocksource_apbt.mult = div_sc(MSEC_PER_SEC,
|
||||
(unsigned long) apbt_freq, APBT_SHIFT);
|
||||
clocksource_register(&clocksource_apbt);
|
||||
clocksource_register_khz(&clocksource_apbt, (u32)apbt_freq*1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -117,81 +117,6 @@ void __init setup_pit_timer(void)
|
|||
}
|
||||
|
||||
#ifndef CONFIG_X86_64
|
||||
/*
|
||||
* Since the PIT overflows every tick, its not very useful
|
||||
* to just read by itself. So use jiffies to emulate a free
|
||||
* running counter:
|
||||
*/
|
||||
static cycle_t pit_read(struct clocksource *cs)
|
||||
{
|
||||
static int old_count;
|
||||
static u32 old_jifs;
|
||||
unsigned long flags;
|
||||
int count;
|
||||
u32 jifs;
|
||||
|
||||
raw_spin_lock_irqsave(&i8253_lock, flags);
|
||||
/*
|
||||
* Although our caller may have the read side of xtime_lock,
|
||||
* this is now a seqlock, and we are cheating in this routine
|
||||
* by having side effects on state that we cannot undo if
|
||||
* there is a collision on the seqlock and our caller has to
|
||||
* retry. (Namely, old_jifs and old_count.) So we must treat
|
||||
* jiffies as volatile despite the lock. We read jiffies
|
||||
* before latching the timer count to guarantee that although
|
||||
* the jiffies value might be older than the count (that is,
|
||||
* the counter may underflow between the last point where
|
||||
* jiffies was incremented and the point where we latch the
|
||||
* count), it cannot be newer.
|
||||
*/
|
||||
jifs = jiffies;
|
||||
outb_pit(0x00, PIT_MODE); /* latch the count ASAP */
|
||||
count = inb_pit(PIT_CH0); /* read the latched count */
|
||||
count |= inb_pit(PIT_CH0) << 8;
|
||||
|
||||
/* VIA686a test code... reset the latch if count > max + 1 */
|
||||
if (count > LATCH) {
|
||||
outb_pit(0x34, PIT_MODE);
|
||||
outb_pit(LATCH & 0xff, PIT_CH0);
|
||||
outb_pit(LATCH >> 8, PIT_CH0);
|
||||
count = LATCH - 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* It's possible for count to appear to go the wrong way for a
|
||||
* couple of reasons:
|
||||
*
|
||||
* 1. The timer counter underflows, but we haven't handled the
|
||||
* resulting interrupt and incremented jiffies yet.
|
||||
* 2. Hardware problem with the timer, not giving us continuous time,
|
||||
* the counter does small "jumps" upwards on some Pentium systems,
|
||||
* (see c't 95/10 page 335 for Neptun bug.)
|
||||
*
|
||||
* Previous attempts to handle these cases intelligently were
|
||||
* buggy, so we just do the simple thing now.
|
||||
*/
|
||||
if (count > old_count && jifs == old_jifs)
|
||||
count = old_count;
|
||||
|
||||
old_count = count;
|
||||
old_jifs = jifs;
|
||||
|
||||
raw_spin_unlock_irqrestore(&i8253_lock, flags);
|
||||
|
||||
count = (LATCH - 1) - count;
|
||||
|
||||
return (cycle_t)(jifs * LATCH) + count;
|
||||
}
|
||||
|
||||
static struct clocksource pit_cs = {
|
||||
.name = "pit",
|
||||
.rating = 110,
|
||||
.read = pit_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.mult = 0,
|
||||
.shift = 20,
|
||||
};
|
||||
|
||||
static int __init init_pit_clocksource(void)
|
||||
{
|
||||
/*
|
||||
|
@ -205,10 +130,7 @@ static int __init init_pit_clocksource(void)
|
|||
pit_ce.mode != CLOCK_EVT_MODE_PERIODIC)
|
||||
return 0;
|
||||
|
||||
pit_cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, pit_cs.shift);
|
||||
|
||||
return clocksource_register(&pit_cs);
|
||||
return clocksource_i8253_init();
|
||||
}
|
||||
arch_initcall(init_pit_clocksource);
|
||||
|
||||
#endif /* !CONFIG_X86_64 */
|
||||
|
|
|
@ -26,8 +26,6 @@
|
|||
#include <asm/x86_init.h>
|
||||
#include <asm/reboot.h>
|
||||
|
||||
#define KVM_SCALE 22
|
||||
|
||||
static int kvmclock = 1;
|
||||
static int msr_kvm_system_time = MSR_KVM_SYSTEM_TIME;
|
||||
static int msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK;
|
||||
|
@ -120,8 +118,6 @@ static struct clocksource kvm_clock = {
|
|||
.read = kvm_clock_get_cycles,
|
||||
.rating = 400,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.mult = 1 << KVM_SCALE,
|
||||
.shift = KVM_SCALE,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
|
@ -203,7 +199,7 @@ void __init kvmclock_init(void)
|
|||
machine_ops.crash_shutdown = kvm_crash_shutdown;
|
||||
#endif
|
||||
kvm_get_preset_lpj();
|
||||
clocksource_register(&kvm_clock);
|
||||
clocksource_register_hz(&kvm_clock, NSEC_PER_SEC);
|
||||
pv_info.paravirt_enabled = 1;
|
||||
pv_info.name = "KVM";
|
||||
|
||||
|
|
|
@ -913,8 +913,6 @@ static struct clocksource lguest_clock = {
|
|||
.rating = 200,
|
||||
.read = lguest_clock_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.mult = 1 << 22,
|
||||
.shift = 22,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
|
@ -997,7 +995,7 @@ static void lguest_time_init(void)
|
|||
/* Set up the timer interrupt (0) to go to our simple timer routine */
|
||||
irq_set_handler(0, lguest_time_irq);
|
||||
|
||||
clocksource_register(&lguest_clock);
|
||||
clocksource_register_hz(&lguest_clock, NSEC_PER_SEC);
|
||||
|
||||
/* We can't set cpumask in the initializer: damn C limitations! Set it
|
||||
* here and register our timer device. */
|
||||
|
|
|
@ -40,7 +40,6 @@ static struct clocksource clocksource_uv = {
|
|||
.rating = 400,
|
||||
.read = uv_read_rtc,
|
||||
.mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
|
||||
.shift = 10,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
|
@ -372,14 +371,11 @@ static __init int uv_rtc_setup_clock(void)
|
|||
if (!is_uv_system())
|
||||
return -ENODEV;
|
||||
|
||||
clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
|
||||
clocksource_uv.shift);
|
||||
|
||||
/* If single blade, prefer tsc */
|
||||
if (uv_num_possible_blades() == 1)
|
||||
clocksource_uv.rating = 250;
|
||||
|
||||
rc = clocksource_register(&clocksource_uv);
|
||||
rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
|
||||
if (rc)
|
||||
printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
|
||||
else
|
||||
|
|
|
@ -26,8 +26,6 @@
|
|||
|
||||
#include "xen-ops.h"
|
||||
|
||||
#define XEN_SHIFT 22
|
||||
|
||||
/* Xen may fire a timer up to this many ns early */
|
||||
#define TIMER_SLOP 100000
|
||||
#define NS_PER_TICK (1000000000LL / HZ)
|
||||
|
@ -211,8 +209,6 @@ static struct clocksource xen_clocksource __read_mostly = {
|
|||
.rating = 400,
|
||||
.read = xen_clocksource_get_cycles,
|
||||
.mask = ~0,
|
||||
.mult = 1<<XEN_SHIFT, /* time directly in nanoseconds */
|
||||
.shift = XEN_SHIFT,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
|
@ -448,7 +444,7 @@ static void __init xen_time_init(void)
|
|||
int cpu = smp_processor_id();
|
||||
struct timespec tp;
|
||||
|
||||
clocksource_register(&xen_clocksource);
|
||||
clocksource_register_hz(&xen_clocksource, NSEC_PER_SEC);
|
||||
|
||||
if (HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL) == 0) {
|
||||
/* Successfully turned off 100Hz tick, so we have the
|
||||
|
|
|
@ -119,4 +119,7 @@ source "drivers/platform/Kconfig"
|
|||
source "drivers/clk/Kconfig"
|
||||
|
||||
source "drivers/hwspinlock/Kconfig"
|
||||
|
||||
source "drivers/clocksource/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -84,8 +84,6 @@ static struct clocksource clocksource_hpet = {
|
|||
.rating = 250,
|
||||
.read = read_hpet,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.mult = 0, /* to be calculated */
|
||||
.shift = 10,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
static struct clocksource *hpet_clocksource;
|
||||
|
@ -934,9 +932,7 @@ int hpet_alloc(struct hpet_data *hdp)
|
|||
if (!hpet_clocksource) {
|
||||
hpet_mctr = (void __iomem *)&hpetp->hp_hpet->hpet_mc;
|
||||
CLKSRC_FSYS_MMIO_SET(clocksource_hpet.fsys_mmio, hpet_mctr);
|
||||
clocksource_hpet.mult = clocksource_hz2mult(hpetp->hp_tick_freq,
|
||||
clocksource_hpet.shift);
|
||||
clocksource_register(&clocksource_hpet);
|
||||
clocksource_register_hz(&clocksource_hpet, hpetp->hp_tick_freq);
|
||||
hpetp->hp_clocksource = &clocksource_hpet;
|
||||
hpet_clocksource = &clocksource_hpet;
|
||||
}
|
||||
|
|
2
drivers/clocksource/Kconfig
Normal file
2
drivers/clocksource/Kconfig
Normal file
|
@ -0,0 +1,2 @@
|
|||
config CLKSRC_I8253
|
||||
bool
|
|
@ -6,3 +6,4 @@ obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
|
|||
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
|
||||
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
|
||||
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
|
||||
obj-$(CONFIG_CLKSRC_I8253) += i8253.o
|
||||
|
|
|
@ -29,8 +29,6 @@ static struct clocksource clocksource_cyclone = {
|
|||
.rating = 250,
|
||||
.read = read_cyclone,
|
||||
.mask = CYCLONE_TIMER_MASK,
|
||||
.mult = 10,
|
||||
.shift = 0,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
|
@ -108,12 +106,8 @@ static int __init init_cyclone_clocksource(void)
|
|||
}
|
||||
cyclone_ptr = cyclone_timer;
|
||||
|
||||
/* sort out mult/shift values: */
|
||||
clocksource_cyclone.shift = 22;
|
||||
clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
|
||||
clocksource_cyclone.shift);
|
||||
|
||||
return clocksource_register(&clocksource_cyclone);
|
||||
return clocksource_register_hz(&clocksource_cyclone,
|
||||
CYCLONE_TIMER_FREQ);
|
||||
}
|
||||
|
||||
arch_initcall(init_cyclone_clocksource);
|
||||
|
|
88
drivers/clocksource/i8253.c
Normal file
88
drivers/clocksource/i8253.c
Normal file
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* i8253 PIT clocksource
|
||||
*/
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/timex.h>
|
||||
|
||||
#include <asm/i8253.h>
|
||||
|
||||
/*
|
||||
* Since the PIT overflows every tick, its not very useful
|
||||
* to just read by itself. So use jiffies to emulate a free
|
||||
* running counter:
|
||||
*/
|
||||
static cycle_t i8253_read(struct clocksource *cs)
|
||||
{
|
||||
static int old_count;
|
||||
static u32 old_jifs;
|
||||
unsigned long flags;
|
||||
int count;
|
||||
u32 jifs;
|
||||
|
||||
raw_spin_lock_irqsave(&i8253_lock, flags);
|
||||
/*
|
||||
* Although our caller may have the read side of xtime_lock,
|
||||
* this is now a seqlock, and we are cheating in this routine
|
||||
* by having side effects on state that we cannot undo if
|
||||
* there is a collision on the seqlock and our caller has to
|
||||
* retry. (Namely, old_jifs and old_count.) So we must treat
|
||||
* jiffies as volatile despite the lock. We read jiffies
|
||||
* before latching the timer count to guarantee that although
|
||||
* the jiffies value might be older than the count (that is,
|
||||
* the counter may underflow between the last point where
|
||||
* jiffies was incremented and the point where we latch the
|
||||
* count), it cannot be newer.
|
||||
*/
|
||||
jifs = jiffies;
|
||||
outb_pit(0x00, PIT_MODE); /* latch the count ASAP */
|
||||
count = inb_pit(PIT_CH0); /* read the latched count */
|
||||
count |= inb_pit(PIT_CH0) << 8;
|
||||
|
||||
/* VIA686a test code... reset the latch if count > max + 1 */
|
||||
if (count > LATCH) {
|
||||
outb_pit(0x34, PIT_MODE);
|
||||
outb_pit(PIT_LATCH & 0xff, PIT_CH0);
|
||||
outb_pit(PIT_LATCH >> 8, PIT_CH0);
|
||||
count = PIT_LATCH - 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* It's possible for count to appear to go the wrong way for a
|
||||
* couple of reasons:
|
||||
*
|
||||
* 1. The timer counter underflows, but we haven't handled the
|
||||
* resulting interrupt and incremented jiffies yet.
|
||||
* 2. Hardware problem with the timer, not giving us continuous time,
|
||||
* the counter does small "jumps" upwards on some Pentium systems,
|
||||
* (see c't 95/10 page 335 for Neptun bug.)
|
||||
*
|
||||
* Previous attempts to handle these cases intelligently were
|
||||
* buggy, so we just do the simple thing now.
|
||||
*/
|
||||
if (count > old_count && jifs == old_jifs)
|
||||
count = old_count;
|
||||
|
||||
old_count = count;
|
||||
old_jifs = jifs;
|
||||
|
||||
raw_spin_unlock_irqrestore(&i8253_lock, flags);
|
||||
|
||||
count = (PIT_LATCH - 1) - count;
|
||||
|
||||
return (cycle_t)(jifs * PIT_LATCH) + count;
|
||||
}
|
||||
|
||||
static struct clocksource i8253_cs = {
|
||||
.name = "pit",
|
||||
.rating = 110,
|
||||
.read = i8253_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
};
|
||||
|
||||
int __init clocksource_i8253_init(void)
|
||||
{
|
||||
return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
|
||||
}
|
|
@ -161,7 +161,7 @@ struct clocksource {
|
|||
/*
|
||||
* First part of structure is read mostly
|
||||
*/
|
||||
char *name;
|
||||
const char *name;
|
||||
struct list_head list;
|
||||
int rating;
|
||||
cycle_t (*read)(struct clocksource *cs);
|
||||
|
@ -341,4 +341,6 @@ static inline void update_vsyscall_tz(void)
|
|||
|
||||
extern void timekeeping_notify(struct clocksource *clock);
|
||||
|
||||
extern int clocksource_i8253_init(void);
|
||||
|
||||
#endif /* _LINUX_CLOCKSOURCE_H */
|
||||
|
|
Loading…
Reference in a new issue