powerpc/perf_event: Fix oops due to perf_event_do_pending call
Anton Blanchard found that large POWER systems would occasionally crash in the exception exit path when profiling with perf_events. The symptom was that an interrupt would occur late in the exit path when the MSR[RI] (recoverable interrupt) bit was clear. Interrupts should be hard-disabled at this point but they were enabled. Because the interrupt was not recoverable the system panicked. The reason is that the exception exit path was calling perf_event_do_pending after hard-disabling interrupts, and perf_event_do_pending will re-enable interrupts. The simplest and cleanest fix for this is to use the same mechanism that 32-bit powerpc does, namely to cause a self-IPI by setting the decrementer to 1. This means we can remove the tests in the exception exit path and raw_local_irq_restore. This also makes sure that the call to perf_event_do_pending from timer_interrupt() happens within irq_enter/irq_exit. (Note that calling perf_event_do_pending from timer_interrupt does not mean that there is a possible 1/HZ latency; setting the decrementer to 1 ensures that the timer interrupt will happen immediately, i.e. within one timebase tick, which is a few nanoseconds or 10s of nanoseconds.) Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: stable@kernel.org Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -130,43 +130,5 @@ static inline int irqs_disabled_flags(unsigned long flags)
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*/
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struct irq_chip;
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#ifdef CONFIG_PERF_EVENTS
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#ifdef CONFIG_PPC64
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static inline unsigned long test_perf_event_pending(void)
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{
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unsigned long x;
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asm volatile("lbz %0,%1(13)"
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: "=r" (x)
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: "i" (offsetof(struct paca_struct, perf_event_pending)));
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return x;
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}
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static inline void set_perf_event_pending(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (1),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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static inline void clear_perf_event_pending(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (0),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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#endif /* CONFIG_PPC64 */
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#else /* CONFIG_PERF_EVENTS */
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static inline unsigned long test_perf_event_pending(void)
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{
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return 0;
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}
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static inline void clear_perf_event_pending(void) {}
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#endif /* CONFIG_PERF_EVENTS */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_HW_IRQ_H */
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@ -133,7 +133,6 @@ int main(void)
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DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
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DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
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DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
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DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_event_pending));
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DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
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#ifdef CONFIG_PPC_MM_SLICES
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DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
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@ -556,15 +556,6 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
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2:
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TRACE_AND_RESTORE_IRQ(r5);
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#ifdef CONFIG_PERF_EVENTS
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/* check paca->perf_event_pending if we're enabling ints */
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lbz r3,PACAPERFPEND(r13)
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and. r3,r3,r5
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beq 27f
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bl .perf_event_do_pending
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27:
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#endif /* CONFIG_PERF_EVENTS */
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/* extract EE bit and use it to restore paca->hard_enabled */
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ld r3,_MSR(r1)
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rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
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@ -53,7 +53,6 @@
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#include <linux/bootmem.h>
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#include <linux/pci.h>
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#include <linux/debugfs.h>
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#include <linux/perf_event.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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@ -145,11 +144,6 @@ notrace void raw_local_irq_restore(unsigned long en)
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}
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#endif /* CONFIG_PPC_STD_MMU_64 */
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if (test_perf_event_pending()) {
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clear_perf_event_pending();
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perf_event_do_pending();
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}
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/*
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* if (get_paca()->hard_enabled) return;
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* But again we need to take care that gcc gets hard_enabled directly
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@ -532,25 +532,60 @@ void __init iSeries_time_init_early(void)
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}
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#endif /* CONFIG_PPC_ISERIES */
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_PPC32)
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DEFINE_PER_CPU(u8, perf_event_pending);
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#ifdef CONFIG_PERF_EVENTS
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void set_perf_event_pending(void)
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/*
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* 64-bit uses a byte in the PACA, 32-bit uses a per-cpu variable...
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*/
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#ifdef CONFIG_PPC64
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static inline unsigned long test_perf_event_pending(void)
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{
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get_cpu_var(perf_event_pending) = 1;
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set_dec(1);
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put_cpu_var(perf_event_pending);
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unsigned long x;
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asm volatile("lbz %0,%1(13)"
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: "=r" (x)
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: "i" (offsetof(struct paca_struct, perf_event_pending)));
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return x;
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}
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static inline void set_perf_event_pending_flag(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (1),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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static inline void clear_perf_event_pending(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (0),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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#else /* 32-bit */
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DEFINE_PER_CPU(u8, perf_event_pending);
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#define set_perf_event_pending_flag() __get_cpu_var(perf_event_pending) = 1
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#define test_perf_event_pending() __get_cpu_var(perf_event_pending)
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#define clear_perf_event_pending() __get_cpu_var(perf_event_pending) = 0
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#else /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
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#endif /* 32 vs 64 bit */
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void set_perf_event_pending(void)
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{
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preempt_disable();
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set_perf_event_pending_flag();
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set_dec(1);
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preempt_enable();
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}
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#else /* CONFIG_PERF_EVENTS */
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#define test_perf_event_pending() 0
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#define clear_perf_event_pending()
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#endif /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
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#endif /* CONFIG_PERF_EVENTS */
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/*
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* For iSeries shared processors, we have to let the hypervisor
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@ -582,10 +617,6 @@ void timer_interrupt(struct pt_regs * regs)
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set_dec(DECREMENTER_MAX);
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#ifdef CONFIG_PPC32
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if (test_perf_event_pending()) {
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clear_perf_event_pending();
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perf_event_do_pending();
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}
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if (atomic_read(&ppc_n_lost_interrupts) != 0)
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do_IRQ(regs);
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#endif
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@ -604,6 +635,11 @@ void timer_interrupt(struct pt_regs * regs)
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calculate_steal_time();
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if (test_perf_event_pending()) {
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clear_perf_event_pending();
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perf_event_do_pending();
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}
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#ifdef CONFIG_PPC_ISERIES
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if (firmware_has_feature(FW_FEATURE_ISERIES))
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get_lppaca()->int_dword.fields.decr_int = 0;
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