MIPS: io: Add barrier after register read in inX()
commitpull/10/head18f3e95b90
upstream. While a barrier is present in the outX() functions before the register write, a similar barrier is missing in the inX() functions after the register read. This could allow memory accesses following inX() to observe stale data. This patch is very similar to commita1cc7034e3
("MIPS: io: Add barrier after register read in readX()"). Because war_io_reorder_wmb() is both used by writeX() and outX(), if readX() need a barrier then so does inX(). Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> Patchwork: https://patchwork.linux-mips.org/patch/19516/ Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: James Hogan <james.hogan@mips.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent
93e1297f9e
commit
0fe95015fb
|
@ -414,6 +414,8 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
|
|||
__val = *__addr; \
|
||||
slow; \
|
||||
\
|
||||
/* prevent prefetching of coherent DMA data prematurely */ \
|
||||
rmb(); \
|
||||
return pfx##ioswab##bwlq(__addr, __val); \
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue