Merge branch 'pci/resource' into next
* pci/resource: PCI: Fail pci_map_rom() if the option ROM is invalid PCI: Move pci_map_rom() error path x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f) PCI: Add pci_resize_resource() for resizing BARs PCI: Add resizable BAR infrastructure PCI: Add PCI resource type mask #definezero-colors
Bjorn Helgaas
commit
104d1e40cf
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@ -635,3 +635,88 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8)
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#define AMD_141b_MMIO_BASE_RE_MASK BIT(0)
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#define AMD_141b_MMIO_BASE_WE_MASK BIT(1)
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#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8)
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#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8)
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#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8)
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#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4)
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#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0)
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#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16
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#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16)
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/*
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* The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow
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* configuring host bridge windows using the _PRS and _SRS methods.
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*
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* But this is rarely implemented, so we manually enable a large 64bit BAR for
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* PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
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* here.
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*/
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static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
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{
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unsigned i;
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u32 base, limit, high;
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struct resource *res, *conflict;
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for (i = 0; i < 8; i++) {
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pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
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pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
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/* Is this slot free? */
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if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
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AMD_141b_MMIO_BASE_WE_MASK)))
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break;
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base >>= 8;
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base |= high << 24;
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/* Abort if a slot already configures a 64bit BAR. */
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if (base > 0x10000)
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return;
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}
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if (i == 8)
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return;
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res = kzalloc(sizeof(*res), GFP_KERNEL);
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if (!res)
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return;
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res->name = "PCI Bus 0000:00";
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res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
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IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
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res->start = 0x100000000ull;
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res->end = 0xfd00000000ull - 1;
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/* Just grab the free area behind system memory for this */
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while ((conflict = request_resource_conflict(&iomem_resource, res)))
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res->start = conflict->end + 1;
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dev_info(&dev->dev, "adding root bus resource %pR\n", res);
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base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
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AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
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limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;
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high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |
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((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)
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& AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK);
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pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
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pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
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pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
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pci_bus_add_resource(dev->bus, res, 0);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
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#endif
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@ -2965,6 +2965,107 @@ bool pci_acs_path_enabled(struct pci_dev *start,
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return true;
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}
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/**
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* pci_rebar_find_pos - find position of resize ctrl reg for BAR
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* @pdev: PCI device
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* @bar: BAR to find
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*
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* Helper to find the position of the ctrl register for a BAR.
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* Returns -ENOTSUPP if resizable BARs are not supported at all.
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* Returns -ENOENT if no ctrl register for the BAR could be found.
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*/
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static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
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{
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unsigned int pos, nbars, i;
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u32 ctrl;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
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if (!pos)
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return -ENOTSUPP;
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pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
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nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
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PCI_REBAR_CTRL_NBAR_SHIFT;
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for (i = 0; i < nbars; i++, pos += 8) {
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int bar_idx;
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pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
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bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
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if (bar_idx == bar)
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return pos;
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}
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return -ENOENT;
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}
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/**
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* pci_rebar_get_possible_sizes - get possible sizes for BAR
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* @pdev: PCI device
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* @bar: BAR to query
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*
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* Get the possible sizes of a resizable BAR as bitmask defined in the spec
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* (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
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*/
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u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
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{
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int pos;
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u32 cap;
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pos = pci_rebar_find_pos(pdev, bar);
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if (pos < 0)
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return 0;
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pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
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return (cap & PCI_REBAR_CAP_SIZES) >> 4;
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}
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/**
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* pci_rebar_get_current_size - get the current size of a BAR
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* @pdev: PCI device
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* @bar: BAR to set size to
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*
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* Read the size of a BAR from the resizable BAR config.
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* Returns size if found or negative error code.
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*/
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int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
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{
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int pos;
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u32 ctrl;
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pos = pci_rebar_find_pos(pdev, bar);
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if (pos < 0)
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return pos;
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pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
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return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
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}
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/**
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* pci_rebar_set_size - set a new size for a BAR
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* @pdev: PCI device
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* @bar: BAR to set size to
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* @size: new size as defined in the spec (0=1MB, 19=512GB)
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*
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* Set the new size of a BAR as defined in the spec.
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* Returns zero if resizing was successful, error code otherwise.
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*/
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int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
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{
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int pos;
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u32 ctrl;
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pos = pci_rebar_find_pos(pdev, bar);
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if (pos < 0)
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return pos;
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pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
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ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
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ctrl |= size << 8;
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pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
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return 0;
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}
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/**
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* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
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* @dev: the PCI device
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@ -366,4 +366,12 @@ int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
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struct resource *res);
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#endif
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u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
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int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
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int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
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static inline u64 pci_rebar_size_to_bytes(int size)
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{
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return 1ULL << (size + 20);
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}
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#endif /* DRIVERS_PCI_H */
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@ -147,12 +147,8 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
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return NULL;
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rom = ioremap(start, *size);
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if (!rom) {
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/* restore enable if ioremap fails */
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if (!(res->flags & IORESOURCE_ROM_ENABLE))
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pci_disable_rom(pdev);
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return NULL;
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}
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if (!rom)
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goto err_ioremap;
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/*
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* Try to find the true size of the ROM since sometimes the PCI window
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@ -160,7 +156,18 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
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* True size is important if the ROM is going to be copied.
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*/
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*size = pci_get_rom_size(pdev, rom, *size);
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if (!*size)
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goto invalid_rom;
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return rom;
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invalid_rom:
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iounmap(rom);
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err_ioremap:
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/* restore enable if ioremap fails */
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if (!(res->flags & IORESOURCE_ROM_ENABLE))
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pci_disable_rom(pdev);
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return NULL;
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}
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EXPORT_SYMBOL(pci_map_rom);
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@ -1518,13 +1518,16 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
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break;
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}
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}
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#define PCI_RES_TYPE_MASK \
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(IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
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IORESOURCE_MEM_64)
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static void pci_bridge_release_resources(struct pci_bus *bus,
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unsigned long type)
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{
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struct pci_dev *dev = bus->self;
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struct resource *r;
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unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
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IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
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unsigned old_flags = 0;
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struct resource *b_res;
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int idx = 1;
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@ -1567,7 +1570,7 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
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*/
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release_child_resources(r);
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if (!release_resource(r)) {
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type = old_flags = r->flags & type_mask;
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type = old_flags = r->flags & PCI_RES_TYPE_MASK;
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dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
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PCI_BRIDGE_RESOURCES + idx, r);
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/* keep the old size */
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@ -1758,8 +1761,6 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
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enum release_type rel_type = leaf_only;
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LIST_HEAD(fail_head);
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struct pci_dev_resource *fail_res;
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unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
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IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
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int pci_try_num = 1;
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enum enable_type enable_local;
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@ -1818,7 +1819,7 @@ again:
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*/
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list_for_each_entry(fail_res, &fail_head, list)
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pci_bus_release_bridge_resources(fail_res->dev->bus,
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fail_res->flags & type_mask,
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fail_res->flags & PCI_RES_TYPE_MASK,
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rel_type);
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/* restore size and flags */
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||||
|
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@ -2031,8 +2032,6 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
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LIST_HEAD(fail_head);
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struct pci_dev_resource *fail_res;
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int retval;
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unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
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IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
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||||
|
||||
again:
|
||||
__pci_bus_size_bridges(parent, &add_list);
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||||
|
|
@ -2066,7 +2065,7 @@ again:
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|||
*/
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list_for_each_entry(fail_res, &fail_head, list)
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pci_bus_release_bridge_resources(fail_res->dev->bus,
|
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fail_res->flags & type_mask,
|
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fail_res->flags & PCI_RES_TYPE_MASK,
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whole_subtree);
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/* restore size and flags */
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||||
|
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@ -2091,6 +2090,104 @@ enable_all:
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|||
}
|
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EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
|
||||
|
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int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
|
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{
|
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struct pci_dev_resource *dev_res;
|
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struct pci_dev *next;
|
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LIST_HEAD(saved);
|
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LIST_HEAD(added);
|
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LIST_HEAD(failed);
|
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unsigned int i;
|
||||
int ret;
|
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|
||||
/* Walk to the root hub, releasing bridge BARs when possible */
|
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next = bridge;
|
||||
do {
|
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bridge = next;
|
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for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
|
||||
i++) {
|
||||
struct resource *res = &bridge->resource[i];
|
||||
|
||||
if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
|
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continue;
|
||||
|
||||
/* Ignore BARs which are still in use */
|
||||
if (res->child)
|
||||
continue;
|
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|
||||
ret = add_to_list(&saved, bridge, res, 0, 0);
|
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if (ret)
|
||||
goto cleanup;
|
||||
|
||||
dev_info(&bridge->dev, "BAR %d: releasing %pR\n",
|
||||
i, res);
|
||||
|
||||
if (res->parent)
|
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release_resource(res);
|
||||
res->start = 0;
|
||||
res->end = 0;
|
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break;
|
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}
|
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if (i == PCI_BRIDGE_RESOURCE_END)
|
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break;
|
||||
|
||||
next = bridge->bus ? bridge->bus->self : NULL;
|
||||
} while (next);
|
||||
|
||||
if (list_empty(&saved))
|
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return -ENOENT;
|
||||
|
||||
__pci_bus_size_bridges(bridge->subordinate, &added);
|
||||
__pci_bridge_assign_resources(bridge, &added, &failed);
|
||||
BUG_ON(!list_empty(&added));
|
||||
|
||||
if (!list_empty(&failed)) {
|
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ret = -ENOSPC;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
list_for_each_entry(dev_res, &saved, list) {
|
||||
/* Skip the bridge we just assigned resources for. */
|
||||
if (bridge == dev_res->dev)
|
||||
continue;
|
||||
|
||||
bridge = dev_res->dev;
|
||||
pci_setup_bridge(bridge->subordinate);
|
||||
}
|
||||
|
||||
free_list(&saved);
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
/* restore size and flags */
|
||||
list_for_each_entry(dev_res, &failed, list) {
|
||||
struct resource *res = dev_res->res;
|
||||
|
||||
res->start = dev_res->start;
|
||||
res->end = dev_res->end;
|
||||
res->flags = dev_res->flags;
|
||||
}
|
||||
free_list(&failed);
|
||||
|
||||
/* Revert to the old configuration */
|
||||
list_for_each_entry(dev_res, &saved, list) {
|
||||
struct resource *res = dev_res->res;
|
||||
|
||||
bridge = dev_res->dev;
|
||||
i = res - bridge->resource;
|
||||
|
||||
res->start = dev_res->start;
|
||||
res->end = dev_res->end;
|
||||
res->flags = dev_res->flags;
|
||||
|
||||
pci_claim_resource(bridge, i);
|
||||
pci_setup_bridge(bridge->subordinate);
|
||||
}
|
||||
free_list(&saved);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
|
|
|
|||
|
|
@ -396,6 +396,64 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz
|
|||
return 0;
|
||||
}
|
||||
|
||||
void pci_release_resource(struct pci_dev *dev, int resno)
|
||||
{
|
||||
struct resource *res = dev->resource + resno;
|
||||
|
||||
dev_info(&dev->dev, "BAR %d: releasing %pR\n", resno, res);
|
||||
release_resource(res);
|
||||
res->end = resource_size(res) - 1;
|
||||
res->start = 0;
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_release_resource);
|
||||
|
||||
int pci_resize_resource(struct pci_dev *dev, int resno, int size)
|
||||
{
|
||||
struct resource *res = dev->resource + resno;
|
||||
int old, ret;
|
||||
u32 sizes;
|
||||
u16 cmd;
|
||||
|
||||
/* Make sure the resource isn't assigned before resizing it. */
|
||||
if (!(res->flags & IORESOURCE_UNSET))
|
||||
return -EBUSY;
|
||||
|
||||
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
||||
if (cmd & PCI_COMMAND_MEMORY)
|
||||
return -EBUSY;
|
||||
|
||||
sizes = pci_rebar_get_possible_sizes(dev, resno);
|
||||
if (!sizes)
|
||||
return -ENOTSUPP;
|
||||
|
||||
if (!(sizes & BIT(size)))
|
||||
return -EINVAL;
|
||||
|
||||
old = pci_rebar_get_current_size(dev, resno);
|
||||
if (old < 0)
|
||||
return old;
|
||||
|
||||
ret = pci_rebar_set_size(dev, resno, size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
|
||||
|
||||
/* Check if the new config works by trying to assign everything. */
|
||||
ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
|
||||
if (ret)
|
||||
goto error_resize;
|
||||
|
||||
return 0;
|
||||
|
||||
error_resize:
|
||||
pci_rebar_set_size(dev, resno, old);
|
||||
res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_resize_resource);
|
||||
|
||||
int pci_enable_resources(struct pci_dev *dev, int mask)
|
||||
{
|
||||
u16 cmd, old_cmd;
|
||||
|
|
|
|||
|
|
@ -1110,6 +1110,8 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
|
|||
void pci_update_resource(struct pci_dev *dev, int resno);
|
||||
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
|
||||
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
|
||||
void pci_release_resource(struct pci_dev *dev, int resno);
|
||||
int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
|
||||
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
|
||||
bool pci_device_is_present(struct pci_dev *pdev);
|
||||
void pci_ignore_hotplug(struct pci_dev *dev);
|
||||
|
|
@ -1189,6 +1191,7 @@ void pci_assign_unassigned_resources(void);
|
|||
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
|
||||
void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
|
||||
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
|
||||
int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
|
||||
void pdev_enable_device(struct pci_dev *);
|
||||
int pci_enable_resources(struct pci_dev *, int mask);
|
||||
void pci_assign_irq(struct pci_dev *dev);
|
||||
|
|
|
|||
|
|
@ -940,9 +940,13 @@
|
|||
#define PCI_SATA_SIZEOF_LONG 16
|
||||
|
||||
/* Resizable BARs */
|
||||
#define PCI_REBAR_CAP 4 /* capability register */
|
||||
#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */
|
||||
#define PCI_REBAR_CTRL 8 /* control register */
|
||||
#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
|
||||
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
|
||||
#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */
|
||||
#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */
|
||||
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */
|
||||
#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */
|
||||
|
||||
/* Dynamic Power Allocation */
|
||||
#define PCI_DPA_CAP 4 /* capability register */
|
||||
|
|
|
|||
Loading…
Reference in New Issue