drivers/cpufreq: Convert some slow-path static_cpu_has() callers to boot_cpu_has()
Using static_cpu_has() is pointless on those paths, convert them to the boot_cpu_has() variant. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -124,7 +124,7 @@ static int __init amd_freq_sensitivity_init(void)
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PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
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if (!pcidev) {
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if (!static_cpu_has(X86_FEATURE_PROC_FEEDBACK))
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if (!boot_cpu_has(X86_FEATURE_PROC_FEEDBACK))
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return -ENODEV;
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}
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@ -527,7 +527,7 @@ static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
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u64 epb;
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int ret;
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if (!static_cpu_has(X86_FEATURE_EPB))
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if (!boot_cpu_has(X86_FEATURE_EPB))
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return -ENXIO;
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ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
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@ -541,7 +541,7 @@ static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
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{
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s16 epp;
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if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
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if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
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/*
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* When hwp_req_data is 0, means that caller didn't read
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* MSR_HWP_REQUEST, so need to read and get EPP.
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@ -566,7 +566,7 @@ static int intel_pstate_set_epb(int cpu, s16 pref)
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u64 epb;
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int ret;
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if (!static_cpu_has(X86_FEATURE_EPB))
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if (!boot_cpu_has(X86_FEATURE_EPB))
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return -ENXIO;
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ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
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@ -614,7 +614,7 @@ static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
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if (epp < 0)
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return epp;
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if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
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if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
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if (epp == HWP_EPP_PERFORMANCE)
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return 1;
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if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
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@ -623,7 +623,7 @@ static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
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return 3;
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else
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return 4;
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} else if (static_cpu_has(X86_FEATURE_EPB)) {
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} else if (boot_cpu_has(X86_FEATURE_EPB)) {
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/*
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* Range:
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* 0x00-0x03 : Performance
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@ -651,7 +651,7 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
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mutex_lock(&intel_pstate_limits_lock);
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if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
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if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
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u64 value;
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ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
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@ -826,7 +826,7 @@ static void intel_pstate_hwp_set(unsigned int cpu)
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epp = cpu_data->epp_powersave;
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}
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update_epp:
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if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
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if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
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value &= ~GENMASK_ULL(31, 24);
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value |= (u64)epp << 24;
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} else {
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@ -851,7 +851,7 @@ static void intel_pstate_hwp_force_min_perf(int cpu)
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value |= HWP_MIN_PERF(min_perf);
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/* Set EPP/EPB to min */
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if (static_cpu_has(X86_FEATURE_HWP_EPP))
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if (boot_cpu_has(X86_FEATURE_HWP_EPP))
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value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
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else
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intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE);
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@ -1241,7 +1241,7 @@ static void __init intel_pstate_sysfs_expose_params(void)
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static void intel_pstate_hwp_enable(struct cpudata *cpudata)
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{
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/* First disable HWP notification interrupt as we don't process them */
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if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
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if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
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wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
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wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
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@ -1178,7 +1178,7 @@ static int powernowk8_init(void)
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unsigned int i, supported_cpus = 0;
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int ret;
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if (static_cpu_has(X86_FEATURE_HW_PSTATE)) {
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if (boot_cpu_has(X86_FEATURE_HW_PSTATE)) {
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__request_acpi_cpufreq();
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return -ENODEV;
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}
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