watchdog: qcom: add support for KPSS WDT
Add a driver for the watchdog timer block found in the Krait Processor Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Josh Cartwright
Wim Van Sebroeck
parent
dfa07141e7
commit
1094ebe9d1
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@ -461,6 +461,19 @@ config TEGRA_WATCHDOG
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To compile this driver as a module, choose M here: the
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module will be called tegra_wdt.
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config QCOM_WDT
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tristate "QCOM watchdog"
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depends on HAS_IOMEM
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depends on ARCH_QCOM
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select WATCHDOG_CORE
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help
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Say Y here to include Watchdog timer support for the watchdog found
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on QCOM chipsets. Currently supported targets are the MSM8960,
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APQ8064, and IPQ8064.
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To compile this driver as a module, choose M here: the
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module will be called qcom_wdt.
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# AVR32 Architecture
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config AT32AP700X_WDT
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@ -58,6 +58,7 @@ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
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obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
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obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
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obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
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obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
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obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
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obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
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186
drivers/watchdog/qcom-wdt.c
Normal file
186
drivers/watchdog/qcom-wdt.c
Normal file
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@ -0,0 +1,186 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#define WDT_RST 0x0
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#define WDT_EN 0x8
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#define WDT_BITE_TIME 0x24
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struct qcom_wdt {
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struct watchdog_device wdd;
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struct clk *clk;
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unsigned long rate;
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void __iomem *base;
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};
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static inline
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struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct qcom_wdt, wdd);
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}
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static int qcom_wdt_start(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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writel(0, wdt->base + WDT_EN);
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writel(1, wdt->base + WDT_RST);
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writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME);
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writel(1, wdt->base + WDT_EN);
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return 0;
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}
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static int qcom_wdt_stop(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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writel(0, wdt->base + WDT_EN);
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return 0;
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}
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static int qcom_wdt_ping(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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writel(1, wdt->base + WDT_RST);
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return 0;
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}
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static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->timeout = timeout;
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return qcom_wdt_start(wdd);
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}
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static const struct watchdog_ops qcom_wdt_ops = {
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.start = qcom_wdt_start,
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.stop = qcom_wdt_stop,
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.ping = qcom_wdt_ping,
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.set_timeout = qcom_wdt_set_timeout,
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.owner = THIS_MODULE,
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};
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static const struct watchdog_info qcom_wdt_info = {
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.options = WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE
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| WDIOF_SETTIMEOUT,
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.identity = KBUILD_MODNAME,
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};
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static int qcom_wdt_probe(struct platform_device *pdev)
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{
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struct qcom_wdt *wdt;
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struct resource *res;
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int ret;
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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wdt->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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wdt->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(wdt->clk)) {
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dev_err(&pdev->dev, "failed to get input clock\n");
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return PTR_ERR(wdt->clk);
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}
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ret = clk_prepare_enable(wdt->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to setup clock\n");
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return ret;
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}
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/*
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* We use the clock rate to calculate the max timeout, so ensure it's
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* not zero to avoid a divide-by-zero exception.
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*
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* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
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* that it would bite before a second elapses it's usefulness is
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* limited. Bail if this is the case.
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*/
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wdt->rate = clk_get_rate(wdt->clk);
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if (wdt->rate == 0 ||
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wdt->rate > 0x10000000U) {
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dev_err(&pdev->dev, "invalid clock rate\n");
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ret = -EINVAL;
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goto err_clk_unprepare;
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}
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wdt->wdd.dev = &pdev->dev;
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wdt->wdd.info = &qcom_wdt_info;
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wdt->wdd.ops = &qcom_wdt_ops;
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wdt->wdd.min_timeout = 1;
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wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
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/*
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* If 'timeout-sec' unspecified in devicetree, assume a 30 second
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* default, unless the max timeout is less than 30 seconds, then use
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* the max instead.
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*/
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wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
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watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
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ret = watchdog_register_device(&wdt->wdd);
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if (ret) {
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dev_err(&pdev->dev, "failed to register watchdog\n");
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goto err_clk_unprepare;
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}
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platform_set_drvdata(pdev, wdt);
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return 0;
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err_clk_unprepare:
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clk_disable_unprepare(wdt->clk);
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return ret;
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}
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static int qcom_wdt_remove(struct platform_device *pdev)
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{
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struct qcom_wdt *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&wdt->wdd);
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clk_disable_unprepare(wdt->clk);
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return 0;
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}
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static const struct of_device_id qcom_wdt_of_table[] = {
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{ .compatible = "qcom,kpss-wdt-msm8960", },
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{ .compatible = "qcom,kpss-wdt-apq8064", },
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{ .compatible = "qcom,kpss-wdt-ipq8064", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
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static struct platform_driver qcom_watchdog_driver = {
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.probe = qcom_wdt_probe,
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.remove = qcom_wdt_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = qcom_wdt_of_table,
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},
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};
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module_platform_driver(qcom_watchdog_driver);
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MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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