[netdrvr b44] trim trailing whitespace
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8056bfafb8
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10badc2154
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@ -137,7 +137,7 @@ static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
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return readl(bp->regs + reg);
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}
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static inline void bw32(const struct b44 *bp,
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static inline void bw32(const struct b44 *bp,
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unsigned long reg, unsigned long val)
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{
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writel(val, bp->regs + reg);
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@ -287,13 +287,13 @@ static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
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val |= ((u32) data[4]) << 8;
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val |= ((u32) data[5]) << 0;
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bw32(bp, B44_CAM_DATA_LO, val);
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val = (CAM_DATA_HI_VALID |
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val = (CAM_DATA_HI_VALID |
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(((u32) data[0]) << 8) |
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(((u32) data[1]) << 0));
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bw32(bp, B44_CAM_DATA_HI, val);
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bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
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(index << CAM_CTRL_INDEX_SHIFT)));
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b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
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b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
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}
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static inline void __b44_disable_ints(struct b44 *bp)
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@ -411,15 +411,15 @@ static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
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static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
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{
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u32 pause_enab = 0;
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u32 pause_enab = 0;
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/* The driver supports only rx pause by default because
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the b44 mac tx pause mechanism generates excessive
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pause frames.
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the b44 mac tx pause mechanism generates excessive
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pause frames.
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Use ethtool to turn on b44 tx pause if necessary.
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*/
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if ((local & ADVERTISE_PAUSE_CAP) &&
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(local & ADVERTISE_PAUSE_ASYM)){
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(local & ADVERTISE_PAUSE_ASYM)){
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if ((remote & LPA_PAUSE_ASYM) &&
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!(remote & LPA_PAUSE_CAP))
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pause_enab |= B44_FLAG_RX_PAUSE;
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@ -1057,7 +1057,7 @@ static int b44_change_mtu(struct net_device *dev, int new_mtu)
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spin_unlock_irq(&bp->lock);
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b44_enable_ints(bp);
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return 0;
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}
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@ -1375,7 +1375,7 @@ static void b44_init_hw(struct b44 *bp)
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bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
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bw32(bp, B44_DMARX_PTR, bp->rx_pending);
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bp->rx_prod = bp->rx_pending;
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bp->rx_prod = bp->rx_pending;
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bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
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@ -1547,9 +1547,9 @@ static void __b44_set_rx_mode(struct net_device *dev)
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val |= RXCONFIG_ALLMULTI;
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else
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i = __b44_load_mcast(bp, dev);
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for (; i < 64; i++) {
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__b44_cam_write(bp, zero, i);
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__b44_cam_write(bp, zero, i);
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}
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bw32(bp, B44_RXCONFIG, val);
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val = br32(bp, B44_CAM_CTRL);
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@ -1731,7 +1731,7 @@ static int b44_set_ringparam(struct net_device *dev,
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spin_unlock_irq(&bp->lock);
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b44_enable_ints(bp);
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return 0;
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}
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@ -1776,7 +1776,7 @@ static int b44_set_pauseparam(struct net_device *dev,
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spin_unlock_irq(&bp->lock);
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b44_enable_ints(bp);
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return 0;
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}
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@ -1892,7 +1892,7 @@ static int __devinit b44_get_invariants(struct b44 *bp)
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bp->core_unit = ssb_core_unit(bp);
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bp->dma_offset = SB_PCI_DMA;
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/* XXX - really required?
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/* XXX - really required?
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bp->flags |= B44_FLAG_BUGGY_TXPTR;
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*/
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out:
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@ -1940,7 +1940,7 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
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"aborting.\n");
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goto err_out_free_res;
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}
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err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
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if (err) {
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printk(KERN_ERR PFX "No usable DMA configuration, "
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@ -2035,9 +2035,9 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
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pci_save_state(bp->pdev);
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/* Chip reset provides power to the b44 MAC & PCI cores, which
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/* Chip reset provides power to the b44 MAC & PCI cores, which
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* is necessary for MAC register access.
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*/
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*/
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b44_chip_reset(bp);
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printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
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@ -2085,10 +2085,10 @@ static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
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del_timer_sync(&bp->timer);
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spin_lock_irq(&bp->lock);
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spin_lock_irq(&bp->lock);
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b44_halt(bp);
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netif_carrier_off(bp->dev);
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netif_carrier_off(bp->dev);
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netif_device_detach(bp->dev);
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b44_free_rings(bp);
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