usb: chipidea: msm: Handle phy power states
The ULPI phy on qcom platforms needs to be initialized and powered on after a USB reset and before we toggle the run/stop bit. Otherwise, the phy locks up and doesn't work properly. Hook the phy initialization into the RESET event and the phy power off into the STOPPED event. Acked-by: Peter Chen <peter.chen@nxp.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Peter Chen <peter.chen@nxp.com>
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@ -80,20 +80,33 @@ static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
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.reset = ci_hdrc_msm_por_reset,
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.reset = ci_hdrc_msm_por_reset,
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};
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};
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static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
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static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
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{
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{
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struct device *dev = ci->dev->parent;
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struct device *dev = ci->dev->parent;
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struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev);
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struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev);
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int ret;
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switch (event) {
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switch (event) {
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case CI_HDRC_CONTROLLER_RESET_EVENT:
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case CI_HDRC_CONTROLLER_RESET_EVENT:
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dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
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dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
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hw_phymode_configure(ci);
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if (msm_ci->secondary_phy) {
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if (msm_ci->secondary_phy) {
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u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL);
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u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL);
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val |= HS_PHY_DIG_CLAMP_N;
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val |= HS_PHY_DIG_CLAMP_N;
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writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
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writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
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}
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}
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ret = phy_init(ci->phy);
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if (ret)
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return ret;
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ret = phy_power_on(ci->phy);
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if (ret) {
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phy_exit(ci->phy);
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return ret;
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}
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/* use AHB transactor, allow posted data writes */
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/* use AHB transactor, allow posted data writes */
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hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);
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hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);
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@ -113,21 +126,18 @@ static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
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HSPHY_SESS_VLD_CTRL);
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HSPHY_SESS_VLD_CTRL);
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}
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}
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usb_phy_init(ci->usb_phy);
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break;
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break;
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case CI_HDRC_CONTROLLER_STOPPED_EVENT:
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case CI_HDRC_CONTROLLER_STOPPED_EVENT:
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dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
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dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
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/*
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phy_power_off(ci->phy);
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* Put the phy in non-driving mode. Otherwise host
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phy_exit(ci->phy);
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* may not detect soft-disconnection.
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*/
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usb_phy_notify_disconnect(ci->usb_phy, USB_SPEED_UNKNOWN);
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break;
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break;
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default:
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default:
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dev_dbg(dev, "unknown ci_hdrc event\n");
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dev_dbg(dev, "unknown ci_hdrc event\n");
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break;
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break;
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}
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}
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return 0;
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}
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}
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static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci,
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static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci,
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@ -167,7 +177,6 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev)
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{
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{
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struct ci_hdrc_msm *ci;
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struct ci_hdrc_msm *ci;
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struct platform_device *plat_ci;
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struct platform_device *plat_ci;
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struct usb_phy *phy;
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struct clk *clk;
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struct clk *clk;
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struct reset_control *reset;
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struct reset_control *reset;
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struct resource *res;
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struct resource *res;
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@ -181,21 +190,12 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev)
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return -ENOMEM;
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return -ENOMEM;
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platform_set_drvdata(pdev, ci);
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platform_set_drvdata(pdev, ci);
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/*
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* OTG(PHY) driver takes care of PHY initialization, clock management,
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* powering up VBUS, mapping of registers address space and power
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* management.
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*/
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phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0);
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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ci->pdata.name = "ci_hdrc_msm";
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ci->pdata.name = "ci_hdrc_msm";
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ci->pdata.capoffset = DEF_CAPOFFSET;
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ci->pdata.capoffset = DEF_CAPOFFSET;
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ci->pdata.flags = CI_HDRC_REGS_SHARED | CI_HDRC_DISABLE_STREAMING |
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ci->pdata.flags = CI_HDRC_REGS_SHARED | CI_HDRC_DISABLE_STREAMING |
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CI_HDRC_OVERRIDE_AHB_BURST;
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CI_HDRC_OVERRIDE_AHB_BURST |
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CI_HDRC_OVERRIDE_PHY_CONTROL;
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ci->pdata.notify_event = ci_hdrc_msm_notify_event;
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ci->pdata.notify_event = ci_hdrc_msm_notify_event;
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ci->pdata.usb_phy = phy;
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reset = devm_reset_control_get(&pdev->dev, "core");
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reset = devm_reset_control_get(&pdev->dev, "core");
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if (IS_ERR(reset))
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if (IS_ERR(reset))
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@ -327,6 +327,7 @@ void hw_phymode_configure(struct ci_hdrc *ci)
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hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
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hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
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}
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}
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}
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}
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EXPORT_SYMBOL_GPL(hw_phymode_configure);
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/**
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/**
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* _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
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* _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
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@ -503,9 +504,12 @@ int hw_device_reset(struct ci_hdrc *ci)
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return ret;
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return ret;
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}
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}
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if (ci->platdata->notify_event)
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if (ci->platdata->notify_event) {
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ci->platdata->notify_event(ci,
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ret = ci->platdata->notify_event(ci,
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CI_HDRC_CONTROLLER_RESET_EVENT);
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CI_HDRC_CONTROLLER_RESET_EVENT);
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if (ret)
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return ret;
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}
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/* USBMODE should be configured step by step */
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/* USBMODE should be configured step by step */
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hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
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hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
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@ -90,8 +90,12 @@ static int ehci_ci_reset(struct usb_hcd *hcd)
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ehci->need_io_watchdog = 0;
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ehci->need_io_watchdog = 0;
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if (ci->platdata->notify_event)
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if (ci->platdata->notify_event) {
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ci->platdata->notify_event(ci, CI_HDRC_CONTROLLER_RESET_EVENT);
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ret = ci->platdata->notify_event(ci,
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CI_HDRC_CONTROLLER_RESET_EVENT);
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if (ret)
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return ret;
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}
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ci_platform_configure(ci);
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ci_platform_configure(ci);
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@ -61,7 +61,7 @@ struct ci_hdrc_platform_data {
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enum usb_dr_mode dr_mode;
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enum usb_dr_mode dr_mode;
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#define CI_HDRC_CONTROLLER_RESET_EVENT 0
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#define CI_HDRC_CONTROLLER_RESET_EVENT 0
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#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
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#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
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void (*notify_event) (struct ci_hdrc *ci, unsigned event);
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int (*notify_event) (struct ci_hdrc *ci, unsigned event);
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struct regulator *reg_vbus;
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struct regulator *reg_vbus;
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struct usb_otg_caps ci_otg_caps;
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struct usb_otg_caps ci_otg_caps;
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bool tpl_support;
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bool tpl_support;
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