arm64: insn: Allow ADD/SUB (immediate) with LSL #12
The encoder for ADD/SUB (immediate) can only cope with 12bit immediates, while there is an encoding for a 12bit immediate shifted by 12 bits to the left. Let's fix this small oversight by allowing the LSL_12 bit to be set. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -35,6 +35,7 @@
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#define AARCH64_INSN_SF_BIT BIT(31)
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#define AARCH64_INSN_N_BIT BIT(22)
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#define AARCH64_INSN_LSL_12 BIT(22)
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static int aarch64_insn_encoding_class[] = {
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AARCH64_INSN_CLS_UNKNOWN,
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@ -903,9 +904,18 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
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return AARCH64_BREAK_FAULT;
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}
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/* We can't encode more than a 24bit value (12bit + 12bit shift) */
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if (imm & ~(BIT(24) - 1))
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goto out;
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/* If we have something in the top 12 bits... */
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if (imm & ~(SZ_4K - 1)) {
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pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
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return AARCH64_BREAK_FAULT;
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/* ... and in the low 12 bits -> error */
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if (imm & (SZ_4K - 1))
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goto out;
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imm >>= 12;
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insn |= AARCH64_INSN_LSL_12;
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}
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
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@ -913,6 +923,10 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
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return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
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out:
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pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
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return AARCH64_BREAK_FAULT;
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}
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u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
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