rtlwifi: Remove the clear interrupt routine from all drivers
Several of these drivers have there TX randomly blocked for 3~5 seconds while measuring tx throughput (iperf). The root couse happens in rtl_pci_flush(). The function uses a while-loop to wait for TX queue length to decrease to 0. The TX queue length counts the number of packets that are queued in the driver. The driver relys on the TX OK interrupt to return skb and reduce TX queue length. The interrupt subroutine disables interupts, reads the interrupt registers, and then clears the registers in the beginning of _rtl_pci_interrupt(). After all interupts process are finished, the driver invokes enable_interrupt() to enable interupts. This behavior is normal for an interrupt subroutine. But enable_interrupt() invokes clear_interrupt() again. This unexpected interrupt clearing may cleari me fresh TX OK interrupts. These missing interrupts cause TX queue length to never reduce to 0i, which causes rtl_pci_flush() to be stuck in unterminated while-loop. This patch removes clear_interrupt() in enable_interrupt() to avoid this behavior. Signed-off-by: Vincent Fann <vincent_fann@realtek.com> Signed-off-by: Shao Fu <shaofu@realtek.com> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Stable <stable@vger.kernel.org> [3.18+] Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -1354,27 +1354,11 @@ void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
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}
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}
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static void rtl88ee_clear_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 tmp;
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tmp = rtl_read_dword(rtlpriv, REG_HISR);
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rtl_write_dword(rtlpriv, REG_HISR, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HISRE);
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rtl_write_dword(rtlpriv, REG_HISRE, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HSISR);
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rtl_write_dword(rtlpriv, REG_HSISR, tmp);
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}
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void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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rtl88ee_clear_interrupt(hw);/*clear it here first*/
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rtl_write_dword(rtlpriv, REG_HIMR,
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rtlpci->irq_mask[0] & 0xFFFFFFFF);
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rtl_write_dword(rtlpriv, REG_HIMRE,
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@ -1584,28 +1584,11 @@ void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
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}
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}
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static void rtl92ee_clear_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 tmp;
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tmp = rtl_read_dword(rtlpriv, REG_HISR);
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rtl_write_dword(rtlpriv, REG_HISR, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HISRE);
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rtl_write_dword(rtlpriv, REG_HISRE, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HSISR);
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rtl_write_dword(rtlpriv, REG_HSISR, tmp);
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}
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void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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rtl92ee_clear_interrupt(hw);/*clear it here first*/
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rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
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rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
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rtlpci->irq_enabled = true;
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@ -1258,18 +1258,6 @@ void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
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}
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}
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static void rtl8723e_clear_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 tmp;
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tmp = rtl_read_dword(rtlpriv, REG_HISR);
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rtl_write_dword(rtlpriv, REG_HISR, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HISRE);
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rtl_write_dword(rtlpriv, REG_HISRE, tmp);
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}
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void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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@ -1284,7 +1272,6 @@ void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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rtl8723e_clear_interrupt(hw);/*clear it here first*/
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rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
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rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
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rtlpci->irq_enabled = false;
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@ -1634,28 +1634,11 @@ void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
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}
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}
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static void rtl8723be_clear_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 tmp;
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tmp = rtl_read_dword(rtlpriv, REG_HISR);
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rtl_write_dword(rtlpriv, REG_HISR, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HISRE);
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rtl_write_dword(rtlpriv, REG_HISRE, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HSISR);
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rtl_write_dword(rtlpriv, REG_HSISR, tmp);
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}
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void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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rtl8723be_clear_interrupt(hw);/*clear it here first*/
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rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
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rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
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rtlpci->irq_enabled = true;
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@ -2253,31 +2253,11 @@ void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
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}
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}
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static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 tmp;
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tmp = rtl_read_dword(rtlpriv, REG_HISR);
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/*printk("clear interrupt first:\n");
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printk("0x%x = 0x%08x\n",REG_HISR, tmp);*/
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rtl_write_dword(rtlpriv, REG_HISR, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HISRE);
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/*printk("0x%x = 0x%08x\n",REG_HISRE, tmp);*/
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rtl_write_dword(rtlpriv, REG_HISRE, tmp);
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tmp = rtl_read_dword(rtlpriv, REG_HSISR);
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/*printk("0x%x = 0x%08x\n",REG_HSISR, tmp);*/
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rtl_write_dword(rtlpriv, REG_HSISR, tmp);
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}
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void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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rtl8821ae_clear_interrupt(hw);/*clear it here first*/
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rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
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rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
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rtlpci->irq_enabled = true;
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