[ALSA] emu10k1 - EMU 1212 with 16 capture channels
* adding 8 more 32-bit capture channels (total of 16) for emu1010 cards * adding some code comments and card details description Signed-off-by: Pavel Hofman <dustin@seznam.cz> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Pavel Hofman
Jaroslav Kysela
parent
15cc4458c5
commit
13d457094b
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@ -1120,6 +1120,16 @@
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/************************************************************************************************/
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/* EMU1010m HANA Destinations */
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/************************************************************************************************/
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/* 32-bit destinations of signal in the Hana FPGA. Destinations are either
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* physical outputs of Hana, or outputs going to Alice2 (audigy) for capture
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* - 16 x EMU_DST_ALICE2_EMU32_X.
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*/
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/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
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/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
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* Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on
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* setup of mixer control for each destination - see emumixer.c -
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* snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
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*/
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#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
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#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
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#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
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@ -1199,6 +1209,12 @@
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/************************************************************************************************/
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/* EMU1010m HANA Sources */
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/************************************************************************************************/
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/* 32-bit sources of signal in the Hana FPGA. The sources are routed to
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* destinations using mixer control for each destination - see emumixer.c
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* Sources are either physical inputs of FPGA,
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* or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
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* 16 x EMU_SRC_ALICE_EMU32B
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*/
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#define EMU_SRC_SILENCE 0x0000 /* Silence */
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#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
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#define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
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@ -694,6 +694,37 @@ static int snd_emu1010_load_firmware(struct snd_emu10k1 * emu, const char * file
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return 0;
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}
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/*
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* EMU-1010 - details found out from this driver, official MS Win drivers,
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* testing the card:
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*
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* Audigy2 (aka Alice2):
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* ---------------------
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* * communication over PCI
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* * conversion of 32-bit data coming over EMU32 links from HANA FPGA
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* to 2 x 16-bit, using internal DSP instructions
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* * slave mode, clock supplied by HANA
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* * linked to HANA using:
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* 32 x 32-bit serial EMU32 output channels
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* 16 x EMU32 input channels
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* (?) x I2S I/O channels (?)
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*
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* FPGA (aka HANA):
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* ---------------
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* * provides all (?) physical inputs and outputs of the card
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* (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
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* * provides clock signal for the card and Alice2
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* * two crystals - for 44.1kHz and 48kHz multiples
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* * provides internal routing of signal sources to signal destinations
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* * inputs/outputs to Alice2 - see above
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*
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* Current status of the driver:
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* ----------------------------
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* * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
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* * PCM device nb. 2:
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* 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops
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* 16 x 32-bit capture - snd_emu10k1_capture_efx_ops
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*/
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static int snd_emu10k1_emu1010_init(struct snd_emu10k1 * emu)
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{
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unsigned int i;
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@ -850,6 +881,27 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 * emu)
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EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
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/* Pavel Hofman - setting defaults for 8 more capture channels
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* Defaults only, users will set their own values anyways, let's
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* just copy/paste.
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*/
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1);
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snd_emu1010_fpga_link_dst_src_write(emu,
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EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1);
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#endif
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#if 0
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/* Original */
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@ -1123,6 +1123,11 @@ snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl
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ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
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}
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/*
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* Used for emu1010 - conversion from 32-bit capture inputs from HANA
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* to 2 x 16-bit registers in audigy - their values are read via DMA.
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* Conversion is performed by Audigy DSP instructions of FX8010.
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*/
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static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
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struct snd_emu10k1_fx8010_code *icode,
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u32 *ptr, int tmp, int bit_shifter16,
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@ -1193,7 +1198,11 @@ static int __devinit _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
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snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
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#if 1
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/* PCM front Playback Volume (independent from stereo mix) */
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/* PCM front Playback Volume (independent from stereo mix)
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* playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
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* where gpr contains attenuation from corresponding mixer control
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* (snd_emu10k1_init_stereo_control)
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*/
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A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
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A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
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snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
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@ -1549,7 +1558,7 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
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if (emu->card_capabilities->emu1010) {
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snd_printk("EMU inputs on\n");
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/* Capture 8 channels of S32_LE sound */
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/* Capture 16 (originally 8) channels of S32_LE sound */
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/* printk("emufx.c: gpr=0x%x, tmp=0x%x\n",gpr, tmp); */
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/* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
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@ -1560,6 +1569,11 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
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snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
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/* Right ADC in 1 of 2 */
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gpr_map[gpr++] = 0x00000000;
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/* Delaying by one sample: instead of copying the input
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* value A_P16VIN to output A_FXBUS2 as in the first channel,
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* we use an auxiliary register, delaying the value by one
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* sample
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*/
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snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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@ -1583,6 +1597,66 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
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/* Pavel Hofman - we still have voices, A_FXBUS2s, and
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* A_P16VINs available -
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* let's add 8 more capture channels - total of 16
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*/
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x10));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x12));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x14));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x16));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x18));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x1a));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x1c));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
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A_C_00000000, A_C_00000000);
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gpr_map[gpr++] = 0x00000000;
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snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
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bit_shifter16,
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A_GPR(gpr - 1),
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A_FXBUS2(0x1e));
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A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
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A_C_00000000, A_C_00000000);
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#if 0
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for (z = 4; z < 8; z++) {
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@ -77,6 +77,10 @@ static int snd_emu10k1_spdif_get_mask(struct snd_kcontrol *kcontrol,
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return 0;
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}
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/*
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* Items labels in enum mixer controls assigning source data to
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* each destination
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*/
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static char *emu1010_src_texts[] = {
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"Silence",
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"Dock Mic A",
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@ -133,6 +137,9 @@ static char *emu1010_src_texts[] = {
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"DSP 31",
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};
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/*
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* List of data sources available for each destination
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*/
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static unsigned int emu1010_src_regs[] = {
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EMU_SRC_SILENCE,/* 0 */
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EMU_SRC_DOCK_MIC_A1, /* 1 */
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@ -189,6 +196,10 @@ static unsigned int emu1010_src_regs[] = {
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EMU_SRC_ALICE_EMU32B+0xf, /* 52 */
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};
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/*
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* Data destinations - physical EMU outputs.
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* Each destination has an enum mixer control to choose a data source
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*/
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static unsigned int emu1010_output_dst[] = {
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EMU_DST_DOCK_DAC1_LEFT1, /* 0 */
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EMU_DST_DOCK_DAC1_RIGHT1, /* 1 */
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@ -216,6 +227,11 @@ static unsigned int emu1010_output_dst[] = {
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EMU_DST_HANA_ADAT+7, /* 23 */
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};
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/*
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* Data destinations - HANA outputs going to Alice2 (audigy) for
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* capture (EMU32 + I2S links)
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* Each destination has an enum mixer control to choose a data source
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*/
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static unsigned int emu1010_input_dst[] = {
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EMU_DST_ALICE2_EMU32_0,
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EMU_DST_ALICE2_EMU32_1,
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@ -1233,24 +1233,26 @@ static int snd_emu10k1_capture_efx_open(struct snd_pcm_substream *substream)
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runtime->hw.rate_min = runtime->hw.rate_max = 48000;
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spin_lock_irq(&emu->reg_lock);
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if (emu->card_capabilities->emu1010) {
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/* TODO
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/* Nb. of channels has been increased to 16 */
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/* TODO
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* SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE
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* SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
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* SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
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* SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000
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* rate_min = 44100,
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* rate_max = 192000,
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* channels_min = 8,
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* channels_max = 8,
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* channels_min = 16,
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* channels_max = 16,
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* Need to add mixer control to fix sample rate
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*
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* There are 16 mono channels of 16bits each.
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* There are 32 mono channels of 16bits each.
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* 24bit Audio uses 2x channels over 16bit
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* 96kHz uses 2x channels over 48kHz
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* 192kHz uses 4x channels over 48kHz
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* So, for 48kHz 24bit, one has 8 channels
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* for 96kHz 24bit, one has 4 channels
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* for 192kHz 24bit, one has 2 channels
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* So, for 48kHz 24bit, one has 16 channels
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* for 96kHz 24bit, one has 8 channels
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* for 192kHz 24bit, one has 4 channels
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*
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*/
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#if 1
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switch (emu->emu1010.internal_clock) {
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@ -1258,13 +1260,15 @@ static int snd_emu10k1_capture_efx_open(struct snd_pcm_substream *substream)
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/* For 44.1kHz */
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runtime->hw.rates = SNDRV_PCM_RATE_44100;
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runtime->hw.rate_min = runtime->hw.rate_max = 44100;
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runtime->hw.channels_min = runtime->hw.channels_max = 8;
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runtime->hw.channels_min =
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runtime->hw.channels_max = 16;
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break;
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case 1:
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/* For 48kHz */
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runtime->hw.rates = SNDRV_PCM_RATE_48000;
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runtime->hw.rate_min = runtime->hw.rate_max = 48000;
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runtime->hw.channels_min = runtime->hw.channels_max = 8;
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runtime->hw.channels_min =
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runtime->hw.channels_max = 16;
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break;
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};
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#endif
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@ -1282,7 +1286,7 @@ static int snd_emu10k1_capture_efx_open(struct snd_pcm_substream *substream)
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#endif
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runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE;
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/* efx_voices_mask[0] is expected to be zero
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* efx_voices_mask[1] is expected to have 16bits set
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* efx_voices_mask[1] is expected to have 32bits set
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*/
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} else {
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runtime->hw.channels_min = runtime->hw.channels_max = 0;
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@ -1787,11 +1791,24 @@ int __devinit snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct s
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/* emu->efx_voices_mask[0] = FXWC_DEFAULTROUTE_C | FXWC_DEFAULTROUTE_A; */
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if (emu->audigy) {
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emu->efx_voices_mask[0] = 0;
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emu->efx_voices_mask[1] = 0xffff;
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if (emu->card_capabilities->emu1010)
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/* Pavel Hofman - 32 voices will be used for
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* capture (write mode) -
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* each bit = corresponding voice
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*/
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emu->efx_voices_mask[1] = 0xffffffff;
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else
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emu->efx_voices_mask[1] = 0xffff;
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} else {
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emu->efx_voices_mask[0] = 0xffff0000;
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||||
emu->efx_voices_mask[1] = 0;
|
||||
}
|
||||
/* For emu1010, the control has to set 32 upper bits (voices)
|
||||
* out of the 64 bits (voices) to true for the 16-channels capture
|
||||
* to work correctly. Correct A_FXWC2 initial value (0xffffffff)
|
||||
* is already defined but the snd_emu10k1_pcm_efx_voices_mask
|
||||
* control can override this register's value.
|
||||
*/
|
||||
kctl = snd_ctl_new1(&snd_emu10k1_pcm_efx_voices_mask, emu);
|
||||
if (!kctl)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
Loading…
Reference in a new issue