Two omap fixes for v4.18-rc cycle
Turns out the recent patches for ARM branch predictor hardening are not working on omap5 and dra7 as planned because the secondary CPU is parked to the bootrom code. We can't configure it in the bootloader. So we must enable invalidates of BTB for omap5 and dra7 secondary core in the kernel. And there's a fix for reserved register access for am3517. The usb otg module on am3517 is not the same as for other omap3. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAltImsMRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXOqNw/7BAD1n1sS2Sq+6QdYLNvWkxlstcarDf29 5jolIQJCaa60WF9C1oTaoy59+UcaiLyk2dWYGgi1ZDce4ihhyIhQUFscHab2Zh0B o4zGXuTnTRBRiCKSI3ue8MTLTpYkuSmoTfWJu3ACEmR0co9J9sHztYz4yd1vj7E6 tWvYLsYv7av4URBNaL4ieeUAZrailRQ3l5vg/+fJ7Xhk1+Ue3bQUmb3DDtypD1Ub OVFVtHGJdxDLaKJ0fhYPIoZYLhIe9BSuxboGrmh/vpyn6kuZ2Q/iWFSyX4kfveoH uEPWzJ6xMe0XNsxyuZ9bYO1rsBrOxXGzZNrgmiLI+GQ4uTK+e68vHPOimtWsNVb1 hMpr8eTiyEUR/lhtMVoizGVPiNnJfhfnbIrUx5g80mAiwogIp9p3IEYHQD2zh4Ly susyjPV9TWoesS1RUrJz2N59qLgSPdOYhmfpaYmc31mVEXu+TiDDxyrUNz++or10 UfJIo/MGDoIWbuRPMRfQEzdJqv13D0FuVbXkgaNWIvAnuDlqQx27dQLDRPepZqS3 kHeOwrxf4h6NrlbCAdF4wn34WLbuMIdpp6rxstGsPi9TVR3PytetBtMlqMkJnfd6 Yg3WcbN695ZNEod1tJhj5E8yUAdYtYPFKSX0egF4z/HrZ4NrjG/JB0gSXXSeS2Q7 X7ecetNHONs= =Wci4 -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.18/fixes-rc4-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Two omap fixes for v4.18-rc cycle Turns out the recent patches for ARM branch predictor hardening are not working on omap5 and dra7 as planned because the secondary CPU is parked to the bootrom code. We can't configure it in the bootloader. So we must enable invalidates of BTB for omap5 and dra7 secondary core in the kernel. And there's a fix for reserved register access for am3517. The usb otg module on am3517 is not the same as for other omap3. * tag 'omap-for-v4.18/fixes-rc4-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am3517.dtsi: Disable reference to OMAP3 OTG controller ARM: DRA7/OMAP5: Enable ACTLR[0] (Enable invalidates of BTB) for secondary cores Signed-off-by: Olof Johansson <olof@lixom.net>
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commit
13e66ceea1
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@ -91,6 +91,11 @@
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};
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};
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};
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};
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/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
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&usb_otg_hs {
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status = "disabled";
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};
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&iva {
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&iva {
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status = "disabled";
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status = "disabled";
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};
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};
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@ -109,6 +109,45 @@ void omap5_erratum_workaround_801819(void)
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static inline void omap5_erratum_workaround_801819(void) { }
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static inline void omap5_erratum_workaround_801819(void) { }
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#endif
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#endif
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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/*
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* Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
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* ICIALLU) to activate the workaround for secondary Core.
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* NOTE: it is assumed that the primary core's configuration is done
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* by the boot loader (kernel will detect a misconfiguration and complain
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* if this is not done).
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*
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* In General Purpose(GP) devices, ACR bit settings can only be done
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* by ROM code in "secure world" using the smc call and there is no
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* option to update the "firmware" on such devices. This also works for
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* High security(HS) devices, as a backup option in case the
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* "update" is not done in the "security firmware".
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*/
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static void omap5_secondary_harden_predictor(void)
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{
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u32 acr, acr_mask;
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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/*
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* ACTLR[0] (Enable invalidates of BTB with ICIALLU)
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*/
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acr_mask = BIT(0);
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/* Do we already have it done.. if yes, skip expensive smc */
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if ((acr & acr_mask) == acr_mask)
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return;
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acr |= acr_mask;
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omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
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pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",
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__func__, smp_processor_id());
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}
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#else
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static inline void omap5_secondary_harden_predictor(void) { }
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#endif
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static void omap4_secondary_init(unsigned int cpu)
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static void omap4_secondary_init(unsigned int cpu)
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{
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{
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/*
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/*
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@ -131,6 +170,8 @@ static void omap4_secondary_init(unsigned int cpu)
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set_cntfreq();
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set_cntfreq();
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/* Configure ACR to disable streaming WA for 801819 */
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/* Configure ACR to disable streaming WA for 801819 */
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omap5_erratum_workaround_801819();
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omap5_erratum_workaround_801819();
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/* Enable ACR to allow for ICUALLU workaround */
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omap5_secondary_harden_predictor();
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}
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}
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/*
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/*
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