RDMA/cxgb4: Zero out ISGL padding
The HW design requires zeroing any pad in SGLs. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -263,6 +263,9 @@ static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
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rem -= len;
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}
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}
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len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
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if (len)
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memset(dstp, 0, len);
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immdp->op = FW_RI_DATA_IMMD;
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immdp->r1 = 0;
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immdp->r2 = 0;
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@ -292,6 +295,7 @@ static int build_isgl(__be64 *queue_start, __be64 *queue_end,
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if (++flitp == queue_end)
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flitp = queue_start;
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}
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*flitp = (__force __be64)0;
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isglp->op = FW_RI_DATA_ISGL;
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isglp->r1 = 0;
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isglp->nsge = cpu_to_be16(num_sge);
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