MIPS: Loongson: Modify ChipConfig register definition
This patch is prepared for Multi-chip interconnection. Since each chip has a ChipConfig register, LOONGSON_CHIPCFG should be an array. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7185/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -249,8 +249,11 @@ static inline void do_perfcnt_IRQ(void)
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#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
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#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
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/* Chip Config */
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#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
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#define MAX_PACKAGES 4
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/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
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extern u64 loongson_chipcfg[MAX_PACKAGES];
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#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
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/* pcimap */
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@ -27,6 +27,8 @@ EXPORT_SYMBOL(cpu_clock_freq);
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struct efi_memory_map_loongson *loongson_memmap;
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struct loongson_system_configuration loongson_sysconf;
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u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
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#define parse_even_earlier(res, option, p) \
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do { \
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unsigned int tmp __maybe_unused; \
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@ -77,6 +79,15 @@ void __init prom_init_env(void)
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cpu_clock_freq = ecpu->cpu_clock_freq;
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loongson_sysconf.cputype = ecpu->cputype;
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if (ecpu->cputype == Loongson_3A) {
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loongson_chipcfg[0] = 0x900000001fe00180;
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loongson_chipcfg[1] = 0x900010001fe00180;
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loongson_chipcfg[2] = 0x900020001fe00180;
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loongson_chipcfg[3] = 0x900030001fe00180;
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} else {
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loongson_chipcfg[0] = 0x900000001fe00180;
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}
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loongson_sysconf.nr_cpus = ecpu->nr_cpus;
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if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
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loongson_sysconf.nr_cpus = NR_CPUS;
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@ -79,7 +79,7 @@ int __weak wakeup_loongson(void)
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static void wait_for_wakeup_events(void)
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{
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while (!wakeup_loongson())
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LOONGSON_CHIPCFG0 &= ~0x7;
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LOONGSON_CHIPCFG(0) &= ~0x7;
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}
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/*
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@ -102,15 +102,15 @@ static void loongson_suspend_enter(void)
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stop_perf_counters();
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cached_cpu_freq = LOONGSON_CHIPCFG0;
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cached_cpu_freq = LOONGSON_CHIPCFG(0);
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/* Put CPU into wait mode */
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LOONGSON_CHIPCFG0 &= ~0x7;
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LOONGSON_CHIPCFG(0) &= ~0x7;
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/* wait for the given events to wakeup cpu from wait mode */
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wait_for_wakeup_events();
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LOONGSON_CHIPCFG0 = cached_cpu_freq;
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LOONGSON_CHIPCFG(0) = cached_cpu_freq;
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mmiowb();
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}
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@ -114,9 +114,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
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clk->rate = rate;
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regval = LOONGSON_CHIPCFG0;
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regval = LOONGSON_CHIPCFG(0);
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regval = (regval & ~0x7) | (pos->driver_data - 1);
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LOONGSON_CHIPCFG0 = regval;
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LOONGSON_CHIPCFG(0) = regval;
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return ret;
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}
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@ -28,7 +28,7 @@ static void reset_cpu(void)
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* reset cpu to full speed, this is needed when enabling cpu frequency
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* scalling
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*/
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LOONGSON_CHIPCFG0 |= 0x7;
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LOONGSON_CHIPCFG(0) |= 0x7;
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}
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/* reset support for fuloong2f */
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@ -399,12 +399,12 @@ static int loongson3_cpu_callback(struct notifier_block *nfb,
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case CPU_POST_DEAD:
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case CPU_POST_DEAD_FROZEN:
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pr_info("Disable clock for CPU#%d\n", cpu);
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LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu));
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LOONGSON_CHIPCFG(0) &= ~(1 << (12 + cpu));
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break;
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case CPU_UP_PREPARE:
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case CPU_UP_PREPARE_FROZEN:
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pr_info("Enable clock for CPU#%d\n", cpu);
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LOONGSON_CHIPCFG0 |= 1 << (12 + cpu);
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LOONGSON_CHIPCFG(0) |= 1 << (12 + cpu);
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break;
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}
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@ -148,9 +148,9 @@ static void loongson2_cpu_wait(void)
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u32 cpu_freq;
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spin_lock_irqsave(&loongson2_wait_lock, flags);
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cpu_freq = LOONGSON_CHIPCFG0;
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LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
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LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
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cpu_freq = LOONGSON_CHIPCFG(0);
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LOONGSON_CHIPCFG(0) &= ~0x7; /* Put CPU into wait mode */
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LOONGSON_CHIPCFG(0) = cpu_freq; /* Restore CPU state */
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spin_unlock_irqrestore(&loongson2_wait_lock, flags);
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local_irq_enable();
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}
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