clk: meson-gxbb: Add EE 32K Clock for CEC
On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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@ -926,6 +926,51 @@ static struct clk_mux gxbb_cts_i958 = {
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},
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};
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static struct clk_divider gxbb_32k_clk_div = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.shift = 0,
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.width = 14,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "32k_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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},
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};
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static struct clk_gate gxbb_32k_clk = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.bit_idx = 15,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "32k_clk_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const char *gxbb_32k_clk_parent_names[] = {
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"xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
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};
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static struct clk_mux gxbb_32k_clk_sel = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.mask = 0x3,
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.shift = 16,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk_sel",
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.ops = &clk_mux_ops,
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.parent_names = gxbb_32k_clk_parent_names,
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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@ -1132,6 +1177,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
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[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
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[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -1251,6 +1299,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
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[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
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[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -1365,6 +1416,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
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&gxbb_mali_1,
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&gxbb_cts_amclk,
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&gxbb_cts_mclk_i958,
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&gxbb_32k_clk,
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};
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static struct clk_mux *const gxbb_clk_muxes[] = {
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@ -1376,6 +1428,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
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&gxbb_cts_amclk_sel,
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&gxbb_cts_mclk_i958_sel,
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&gxbb_cts_i958,
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&gxbb_32k_clk_sel,
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};
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static struct clk_divider *const gxbb_clk_dividers[] = {
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@ -1384,6 +1437,7 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
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&gxbb_mali_0_div,
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&gxbb_mali_1_div,
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&gxbb_cts_mclk_i958_div,
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&gxbb_32k_clk_div,
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};
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static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
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@ -284,8 +284,11 @@
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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/* CLKID_CTS_I958 */
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#define CLKID_32K_CLK 114
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#define CLKID_32K_CLK_SEL 115
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#define CLKID_32K_CLK_DIV 116
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#define NR_CLKS 114
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#define NR_CLKS 117
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/* include the CLKIDs that have been made part of the stable DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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