pciehp: use pci_pcie_cap()
Use pci_pcie_cap() instead of pci_find_capability() to get PCIe capability offset in pciehp driver. This avoids unnecessary search in PCI configuration space. This patch also removes 'cap_base' field in struct controller, that was used to hold PCIe capability offset by pciehp itself. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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1518c17ab7
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@ -91,7 +91,6 @@ struct controller {
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struct slot *slot;
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wait_queue_head_t queue; /* sleep & wake process */
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u32 slot_cap;
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u8 cap_base;
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struct timer_list poll_timer;
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unsigned int cmd_busy:1;
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unsigned int no_cmd_complete:1;
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@ -87,7 +87,8 @@ static int __init dummy_probe(struct pcie_device *dev)
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/* Note: pciehp_detect_mode != PCIEHP_DETECT_ACPI here */
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if (pciehp_get_hp_hw_control_from_firmware(pdev))
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return -ENODEV;
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if (!(pos = pci_find_capability(pdev, PCI_CAP_ID_EXP)))
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pos = pci_pcie_cap(pdev);
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if (!pos)
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return -ENODEV;
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pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap);
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slot = kzalloc(sizeof(*slot), GFP_KERNEL);
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@ -45,25 +45,25 @@ static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
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static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_read_config_word(dev, ctrl->cap_base + reg, value);
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return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
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}
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static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
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return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
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}
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static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_write_config_word(dev, ctrl->cap_base + reg, value);
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return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
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}
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static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
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{
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struct pci_dev *dev = ctrl->pcie->port;
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return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
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return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
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}
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/* Power Control Command */
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@ -318,8 +318,8 @@ int pciehp_get_attention_status(struct slot *slot, u8 *status)
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return retval;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
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@ -356,8 +356,8 @@ int pciehp_get_power_status(struct slot *slot, u8 *status)
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ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
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return retval;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
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@ -442,8 +442,8 @@ int pciehp_set_attention_status(struct slot *slot, u8 value)
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default:
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return -EINVAL;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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}
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@ -456,8 +456,8 @@ void pciehp_green_led_on(struct slot *slot)
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slot_cmd = 0x0100;
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cmd_mask = PCI_EXP_SLTCTL_PIC;
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pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}
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void pciehp_green_led_off(struct slot *slot)
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@ -469,8 +469,8 @@ void pciehp_green_led_off(struct slot *slot)
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slot_cmd = 0x0300;
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cmd_mask = PCI_EXP_SLTCTL_PIC;
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pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}
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void pciehp_green_led_blink(struct slot *slot)
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@ -482,8 +482,8 @@ void pciehp_green_led_blink(struct slot *slot)
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slot_cmd = 0x0200;
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cmd_mask = PCI_EXP_SLTCTL_PIC;
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pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}
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int pciehp_power_on_slot(struct slot * slot)
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@ -525,8 +525,8 @@ int pciehp_power_on_slot(struct slot * slot)
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ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
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return retval;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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ctrl->power_fault_detected = 0;
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return retval;
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@ -552,8 +552,8 @@ int pciehp_power_off_slot(struct slot * slot)
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ctrl_err(ctrl, "Write command failed!\n");
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return retval;
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}
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
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__func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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return 0;
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}
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@ -885,7 +885,8 @@ static inline void dbg_ctrl(struct controller *ctrl)
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pdev->subsystem_device);
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ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
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pdev->subsystem_vendor);
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ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
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ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
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pci_pcie_cap(pdev));
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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if (!pci_resource_len(pdev, i))
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continue;
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@ -929,8 +930,7 @@ struct controller *pcie_init(struct pcie_device *dev)
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goto abort;
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}
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ctrl->pcie = dev;
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ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (!ctrl->cap_base) {
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if (!pci_pcie_cap(pdev)) {
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ctrl_err(ctrl, "Cannot find PCI Express capability\n");
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goto abort_ctrl;
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}
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