Small number of user-visible regression fixes for clock drivers. There
is a memory leak fix for an ST platform, an infinite Loop Of Doom fix for the recent changes to the basic clock divider (hopefully the last fix for those recent changes) and some Tegra PLL changes which keep PCI from being hosed on that platform. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJThtlQAAoJEKI6nJvDJaTU4aUQALJuaJjFli8Q8DX1mBQYIHh6 v1cyLJYBygmFUQ3FWSar7qZMu6ub+uuu/RLOUQfqZheG99imnVulPdeC+SlcEzqm BHiUsIu+rBtveOF0a0f/1G+heuqS5rmv+oHNDUWABekVQ9lwy+1dXkh+4Kw7eA+3 YEX85ypfJuYnGh9aA6/dt9Ldw29RtdXfdeX9LhOCLV5GZ4e61fBcUCoCID4rnzqQ viXkqpbjnONnd0ShtnkN+NsIJTn1bgu13EDLcFFyXDfjNucyhINR1FDveWe1OsaZ iWHZGVgyXRzV8bBgCrjfVtwP4vQlaiACKmF30jffYqkxK+DxdB55hiCER1WpRg37 PrRDFRpzXTT0HHovldvlhoUnpRS3055RO+NiD4hIV6WzhTsbLlz1a5EY0gBQRM4U dLRxnSpVlR2Vfvhkr54Hrc+AT4j/IMnRlZfUQu6MsuQ76YD153BAUwfMffJbuumC iwphEOnJNIcssNeSngDQDJlgXINfucaLnSAjnG01U+qQmFqlqdVWHKTdXRRuW48P cdkYRENm4JzwUIyq9sa1rXtRMd7pNwXCmngmXwNe5z8TdhMiNszHCpR9aY9zCIgC HNIqp1Mqru+1KEUGRzbLo1gy+uy3JbwQSfw603upFga7Xsyjz7qDacjx1g0qe3Wd dp9/GjPKFGD2KydD/XIb =MU0S -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux Pull clock fixes from Mike Turquette: "Small number of user-visible regression fixes for clock drivers. There is a memory leak fix for an ST platform, an infinite Loop Of Doom fix for the recent changes to the basic clock divider (hopefully the last fix for those recent changes) and some Tegra PLL changes which keep PCI from being hosed on that platform" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: st: Fix memory leak clk: divider: Fix table round up function clk: tegra: Fix enabling of PLLE clk: tegra: Introduce divider mask and shift helpers clk: tegra: Fix PLLE programming
This commit is contained in:
commit
15a7b60ea1
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@ -147,7 +147,7 @@ static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
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static int _round_up_table(const struct clk_div_table *table, int div)
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{
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const struct clk_div_table *clkt;
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int up = _get_table_maxdiv(table);
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int up = INT_MAX;
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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@ -521,8 +521,10 @@ static struct clk * __init clkgen_odf_register(const char *parent_name,
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gate->lock = odf_lock;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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if (!div) {
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kfree(gate);
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return ERR_PTR(-ENOMEM);
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}
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div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
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div->reg = reg + pll_data->odf[odf].offset;
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@ -58,9 +58,9 @@
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#define PLLDU_LFCON_SET_DIVN 600
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#define PLLE_BASE_DIVCML_SHIFT 24
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#define PLLE_BASE_DIVCML_WIDTH 4
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#define PLLE_BASE_DIVCML_MASK 0xf
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#define PLLE_BASE_DIVP_SHIFT 16
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#define PLLE_BASE_DIVP_WIDTH 7
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#define PLLE_BASE_DIVP_WIDTH 6
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#define PLLE_BASE_DIVN_SHIFT 8
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#define PLLE_BASE_DIVN_WIDTH 8
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#define PLLE_BASE_DIVM_SHIFT 0
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@ -183,6 +183,14 @@
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#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
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mask(p->params->div_nmp->divp_width))
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#define divm_shift(p) (p)->params->div_nmp->divm_shift
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#define divn_shift(p) (p)->params->div_nmp->divn_shift
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#define divp_shift(p) (p)->params->div_nmp->divp_shift
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#define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
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#define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
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#define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
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#define divm_max(p) (divm_mask(p))
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#define divn_max(p) (divn_mask(p))
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#define divp_max(p) (1 << (divp_mask(p)))
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@ -476,13 +484,12 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
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} else {
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val = pll_readl_base(pll);
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val &= ~((divm_mask(pll) << div_nmp->divm_shift) |
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(divn_mask(pll) << div_nmp->divn_shift) |
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(divp_mask(pll) << div_nmp->divp_shift));
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val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
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divp_mask_shifted(pll));
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val |= ((cfg->m << div_nmp->divm_shift) |
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(cfg->n << div_nmp->divn_shift) |
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(cfg->p << div_nmp->divp_shift));
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val |= (cfg->m << divm_shift(pll)) |
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(cfg->n << divn_shift(pll)) |
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(cfg->p << divp_shift(pll));
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pll_writel_base(val, pll);
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}
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@ -730,11 +737,12 @@ static int clk_plle_enable(struct clk_hw *hw)
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if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
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/* configure dividers */
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val = pll_readl_base(pll);
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val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
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val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
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val |= sel.m << pll->params->div_nmp->divm_shift;
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val |= sel.n << pll->params->div_nmp->divn_shift;
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val |= sel.p << pll->params->div_nmp->divp_shift;
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val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
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divm_mask_shifted(pll));
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val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
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val |= sel.m << divm_shift(pll);
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val |= sel.n << divn_shift(pll);
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val |= sel.p << divp_shift(pll);
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val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
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pll_writel_base(val, pll);
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}
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@ -745,10 +753,11 @@ static int clk_plle_enable(struct clk_hw *hw)
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pll_writel_misc(val, pll);
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val = readl(pll->clk_base + PLLE_SS_CTRL);
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val &= ~PLLE_SS_COEFFICIENTS_MASK;
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val |= PLLE_SS_DISABLE;
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writel(val, pll->clk_base + PLLE_SS_CTRL);
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val |= pll_readl_base(pll);
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val = pll_readl_base(pll);
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val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
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pll_writel_base(val, pll);
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@ -1292,10 +1301,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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pll_writel(val, PLLE_SS_CTRL, pll);
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val = pll_readl_base(pll);
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val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
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val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
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val |= sel.m << pll->params->div_nmp->divm_shift;
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val |= sel.n << pll->params->div_nmp->divn_shift;
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val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
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divm_mask_shifted(pll));
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val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
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val |= sel.m << divm_shift(pll);
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val |= sel.n << divn_shift(pll);
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val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
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pll_writel_base(val, pll);
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udelay(1);
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@ -1410,6 +1420,15 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
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return clk;
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}
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static struct div_nmp pll_e_nmp = {
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.divn_shift = PLLE_BASE_DIVN_SHIFT,
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.divn_width = PLLE_BASE_DIVN_WIDTH,
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.divm_shift = PLLE_BASE_DIVM_SHIFT,
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.divm_width = PLLE_BASE_DIVM_WIDTH,
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.divp_shift = PLLE_BASE_DIVP_SHIFT,
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.divp_width = PLLE_BASE_DIVP_WIDTH,
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};
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struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags, struct tegra_clk_pll_params *pll_params,
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@ -1420,6 +1439,10 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
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pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
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pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
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if (!pll_params->div_nmp)
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pll_params->div_nmp = &pll_e_nmp;
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pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
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if (IS_ERR(pll))
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return ERR_CAST(pll);
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@ -1557,9 +1580,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
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int m;
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m = _pll_fixed_mdiv(pll_params, parent_rate);
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val = m << PLL_BASE_DIVM_SHIFT;
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val |= (pll_params->vco_min / parent_rate)
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<< PLL_BASE_DIVN_SHIFT;
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val = m << divm_shift(pll);
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val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
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pll_writel_base(val, pll);
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}
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