i2c: hix5hd2: add i2c controller driver
I2C drivers for hix5hd2 soc series, including following chipset Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100. Signed-off-by: Wei Yan <sledge.yanwei@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [wsa: folded dt docs into this patch] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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24
Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
Normal file
24
Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
Normal file
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@ -0,0 +1,24 @@
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I2C for Hisilicon hix5hd2 chipset platform
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Required properties:
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- compatible: Must be "hisilicon,hix5hd2-i2c"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: interrupt number to the cpu.
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks: phandles to input clocks.
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Optional properties:
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- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
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- Child nodes conforming to i2c bus binding
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Examples:
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I2C0@f8b10000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0xf8b10000 0x1000>;
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interrupts = <0 38 4>;
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clocks = <&clock HIX5HD2_I2C0_RST>;
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#address-cells = <1>;
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#size-cells = <0>;
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}
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@ -77,6 +77,16 @@ config I2C_AMD8111
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This driver can also be built as a module. If so, the module
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will be called i2c-amd8111.
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config I2C_HIX5HD2
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tristate "Hix5hd2 high-speed I2C driver"
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depends on ARCH_HIX5HD2
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help
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Say Y here to include support for high-speed I2C controller in the
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Hisilicon based hix5hd2 SoCs.
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This driver can also be built as a module. If so, the module
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will be called i2c-hix5hd2.
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config I2C_I801
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tristate "Intel 82801 (ICH/PCH)"
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depends on PCI
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@ -48,6 +48,7 @@ obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
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obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
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obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
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obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
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obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o
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obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
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obj-$(CONFIG_I2C_IMX) += i2c-imx.o
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obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
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557
drivers/i2c/busses/i2c-hix5hd2.c
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557
drivers/i2c/busses/i2c-hix5hd2.c
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@ -0,0 +1,557 @@
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/*
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* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Now only support 7 bit address.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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/* Register Map */
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#define HIX5I2C_CTRL 0x00
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#define HIX5I2C_COM 0x04
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#define HIX5I2C_ICR 0x08
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#define HIX5I2C_SR 0x0c
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#define HIX5I2C_SCL_H 0x10
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#define HIX5I2C_SCL_L 0x14
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#define HIX5I2C_TXR 0x18
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#define HIX5I2C_RXR 0x1c
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/* I2C_CTRL_REG */
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#define I2C_ENABLE BIT(8)
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#define I2C_UNMASK_TOTAL BIT(7)
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#define I2C_UNMASK_START BIT(6)
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#define I2C_UNMASK_END BIT(5)
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#define I2C_UNMASK_SEND BIT(4)
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#define I2C_UNMASK_RECEIVE BIT(3)
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#define I2C_UNMASK_ACK BIT(2)
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#define I2C_UNMASK_ARBITRATE BIT(1)
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#define I2C_UNMASK_OVER BIT(0)
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#define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
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/* I2C_COM_REG */
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#define I2C_NO_ACK BIT(4)
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#define I2C_START BIT(3)
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#define I2C_READ BIT(2)
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#define I2C_WRITE BIT(1)
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#define I2C_STOP BIT(0)
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/* I2C_ICR_REG */
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#define I2C_CLEAR_START BIT(6)
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#define I2C_CLEAR_END BIT(5)
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#define I2C_CLEAR_SEND BIT(4)
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#define I2C_CLEAR_RECEIVE BIT(3)
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#define I2C_CLEAR_ACK BIT(2)
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#define I2C_CLEAR_ARBITRATE BIT(1)
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#define I2C_CLEAR_OVER BIT(0)
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#define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
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I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
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I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
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I2C_CLEAR_OVER)
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/* I2C_SR_REG */
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#define I2C_BUSY BIT(7)
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#define I2C_START_INTR BIT(6)
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#define I2C_END_INTR BIT(5)
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#define I2C_SEND_INTR BIT(4)
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#define I2C_RECEIVE_INTR BIT(3)
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#define I2C_ACK_INTR BIT(2)
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#define I2C_ARBITRATE_INTR BIT(1)
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#define I2C_OVER_INTR BIT(0)
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#define HIX5I2C_MAX_FREQ 400000 /* 400k */
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#define HIX5I2C_READ_OPERATION 0x01
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enum hix5hd2_i2c_state {
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HIX5I2C_STAT_RW_ERR = -1,
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HIX5I2C_STAT_INIT,
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HIX5I2C_STAT_RW,
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HIX5I2C_STAT_SND_STOP,
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HIX5I2C_STAT_RW_SUCCESS,
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};
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struct hix5hd2_i2c_priv {
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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struct completion msg_complete;
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unsigned int msg_idx;
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unsigned int msg_len;
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int stop;
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void __iomem *regs;
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struct clk *clk;
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struct device *dev;
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spinlock_t lock; /* IRQ synchronization */
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int err;
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unsigned int freq;
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enum hix5hd2_i2c_state state;
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};
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static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv)
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{
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u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
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writel_relaxed(val, priv->regs + HIX5I2C_ICR);
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return val;
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}
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static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv)
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{
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writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
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}
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static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv)
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{
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writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
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}
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static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv)
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{
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writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
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priv->regs + HIX5I2C_CTRL);
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}
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static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv)
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{
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u32 rate, val;
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u32 scl, sysclock;
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/* close all i2c interrupt */
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val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
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writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
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rate = priv->freq;
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sysclock = clk_get_rate(priv->clk);
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scl = (sysclock / (rate * 2)) / 2 - 1;
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writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
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writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
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/* restore original interrupt*/
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writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
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dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n",
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__func__, sysclock, rate, scl);
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}
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static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv)
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{
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hix5hd2_i2c_disable_irq(priv);
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hix5hd2_i2c_drv_setrate(priv);
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hix5hd2_i2c_clr_all_irq(priv);
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hix5hd2_i2c_enable_irq(priv);
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}
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static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv)
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{
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clk_disable_unprepare(priv->clk);
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msleep(20);
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clk_prepare_enable(priv->clk);
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hix5hd2_i2c_init(priv);
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}
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static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv)
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{
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unsigned long stop_time;
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u32 int_status;
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/* wait for 100 milli seconds for the bus to be idle */
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stop_time = jiffies + msecs_to_jiffies(100);
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do {
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int_status = hix5hd2_i2c_clr_pend_irq(priv);
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if (!(int_status & I2C_BUSY))
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return 0;
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usleep_range(50, 200);
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} while (time_before(jiffies, stop_time));
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return -EBUSY;
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}
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static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv)
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{
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if (priv->state == HIX5I2C_STAT_SND_STOP)
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dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__);
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else
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dev_dbg(priv->dev, "%s: have not data to send\n", __func__);
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priv->state = HIX5I2C_STAT_RW_SUCCESS;
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priv->err = 0;
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}
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static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv)
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{
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if (priv->stop) {
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priv->state = HIX5I2C_STAT_SND_STOP;
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writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
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} else {
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hix5hd2_rw_over(priv);
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}
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}
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static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv)
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{
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if (priv->msg_len == 1) {
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/* the last byte don't need send ACK */
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writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
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} else if (priv->msg_len > 1) {
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/* if i2c master receive data will send ACK */
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writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
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} else {
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hix5hd2_rw_handle_stop(priv);
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}
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}
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static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv)
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{
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u8 data;
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if (priv->msg_len > 0) {
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data = priv->msg->buf[priv->msg_idx++];
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writel_relaxed(data, priv->regs + HIX5I2C_TXR);
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writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
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} else {
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hix5hd2_rw_handle_stop(priv);
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}
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}
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static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv)
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{
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u8 data;
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if (priv->state == HIX5I2C_STAT_INIT) {
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priv->state = HIX5I2C_STAT_RW;
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} else if (priv->state == HIX5I2C_STAT_RW) {
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if (priv->msg->flags & I2C_M_RD) {
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data = readl_relaxed(priv->regs + HIX5I2C_RXR);
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priv->msg->buf[priv->msg_idx++] = data;
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}
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priv->msg_len--;
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} else {
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dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n",
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__func__, priv->state, priv->msg_len);
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return -EAGAIN;
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}
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return 0;
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}
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static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
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{
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struct hix5hd2_i2c_priv *priv = dev_id;
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u32 int_status;
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int ret;
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spin_lock(&priv->lock);
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int_status = hix5hd2_i2c_clr_pend_irq(priv);
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/* handle error */
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if (int_status & I2C_ARBITRATE_INTR) {
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/* bus error */
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dev_dbg(priv->dev, "ARB bus loss\n");
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priv->err = -EAGAIN;
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priv->state = HIX5I2C_STAT_RW_ERR;
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goto stop;
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} else if (int_status & I2C_ACK_INTR) {
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/* ack error */
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dev_dbg(priv->dev, "No ACK from device\n");
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priv->err = -ENXIO;
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priv->state = HIX5I2C_STAT_RW_ERR;
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goto stop;
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}
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if (int_status & I2C_OVER_INTR) {
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if (priv->msg_len > 0) {
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ret = hix5hd2_rw_preprocess(priv);
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if (ret) {
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priv->err = ret;
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priv->state = HIX5I2C_STAT_RW_ERR;
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goto stop;
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}
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if (priv->msg->flags & I2C_M_RD)
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hix5hd2_read_handle(priv);
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else
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hix5hd2_write_handle(priv);
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} else {
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hix5hd2_rw_over(priv);
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}
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}
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stop:
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if ((priv->state == HIX5I2C_STAT_RW_SUCCESS &&
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priv->msg->len == priv->msg_idx) ||
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(priv->state == HIX5I2C_STAT_RW_ERR)) {
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hix5hd2_i2c_disable_irq(priv);
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hix5hd2_i2c_clr_pend_irq(priv);
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complete(&priv->msg_complete);
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}
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spin_unlock(&priv->lock);
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return IRQ_HANDLED;
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}
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static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop)
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{
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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hix5hd2_i2c_clr_all_irq(priv);
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hix5hd2_i2c_enable_irq(priv);
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if (priv->msg->flags & I2C_M_RD)
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writel_relaxed((priv->msg->addr << 1) | HIX5I2C_READ_OPERATION,
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priv->regs + HIX5I2C_TXR);
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else
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writel_relaxed(priv->msg->addr << 1,
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priv->regs + HIX5I2C_TXR);
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writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv,
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struct i2c_msg *msgs, int stop)
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{
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unsigned long timeout;
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int ret;
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priv->msg = msgs;
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priv->msg_idx = 0;
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priv->msg_len = priv->msg->len;
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priv->stop = stop;
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priv->err = 0;
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priv->state = HIX5I2C_STAT_INIT;
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reinit_completion(&priv->msg_complete);
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hix5hd2_i2c_message_start(priv, stop);
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timeout = wait_for_completion_timeout(&priv->msg_complete,
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priv->adap.timeout);
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if (timeout == 0) {
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priv->state = HIX5I2C_STAT_RW_ERR;
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priv->err = -ETIMEDOUT;
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dev_warn(priv->dev, "%s timeout=%d\n",
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msgs->flags & I2C_M_RD ? "rx" : "tx",
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priv->adap.timeout);
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}
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ret = priv->state;
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/*
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* If this is the last message to be transfered (stop == 1)
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* Then check if the bus can be brought back to idle.
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*/
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if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
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ret = hix5hd2_i2c_wait_bus_idle(priv);
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if (ret < 0)
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hix5hd2_i2c_reset(priv);
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return priv->err;
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}
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|
||||
static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
|
||||
struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap);
|
||||
int i, ret, stop;
|
||||
|
||||
pm_runtime_get_sync(priv->dev);
|
||||
|
||||
for (i = 0; i < num; i++, msgs++) {
|
||||
stop = (i == num - 1);
|
||||
ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (i == num) {
|
||||
ret = num;
|
||||
} else {
|
||||
/* Only one message, cannot access the device */
|
||||
if (i == 1)
|
||||
ret = -EREMOTEIO;
|
||||
else
|
||||
ret = i;
|
||||
|
||||
dev_warn(priv->dev, "xfer message failed\n");
|
||||
}
|
||||
|
||||
out:
|
||||
pm_runtime_mark_last_busy(priv->dev);
|
||||
pm_runtime_put_autosuspend(priv->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
|
||||
.master_xfer = hix5hd2_i2c_xfer,
|
||||
.functionality = hix5hd2_i2c_func,
|
||||
};
|
||||
|
||||
static int hix5hd2_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct hix5hd2_i2c_priv *priv;
|
||||
struct resource *mem;
|
||||
unsigned int freq;
|
||||
int irq, ret;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_property_read_u32(np, "clock-frequency", &freq)) {
|
||||
/* use 100k as default value */
|
||||
priv->freq = 100000;
|
||||
} else {
|
||||
if (freq > HIX5I2C_MAX_FREQ) {
|
||||
priv->freq = HIX5I2C_MAX_FREQ;
|
||||
dev_warn(priv->dev, "use max freq %d instead\n",
|
||||
HIX5I2C_MAX_FREQ);
|
||||
} else {
|
||||
priv->freq = freq;
|
||||
}
|
||||
}
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->regs = devm_ioremap_resource(&pdev->dev, mem);
|
||||
if (IS_ERR(priv->regs))
|
||||
return PTR_ERR(priv->regs);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0) {
|
||||
dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(priv->clk)) {
|
||||
dev_err(&pdev->dev, "cannot get clock\n");
|
||||
return PTR_ERR(priv->clk);
|
||||
}
|
||||
clk_prepare_enable(priv->clk);
|
||||
|
||||
strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
|
||||
priv->dev = &pdev->dev;
|
||||
priv->adap.owner = THIS_MODULE;
|
||||
priv->adap.algo = &hix5hd2_i2c_algorithm;
|
||||
priv->adap.retries = 3;
|
||||
priv->adap.dev.of_node = np;
|
||||
priv->adap.algo_data = priv;
|
||||
priv->adap.dev.parent = &pdev->dev;
|
||||
i2c_set_adapdata(&priv->adap, priv);
|
||||
platform_set_drvdata(pdev, priv);
|
||||
spin_lock_init(&priv->lock);
|
||||
init_completion(&priv->msg_complete);
|
||||
|
||||
hix5hd2_i2c_init(priv);
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq,
|
||||
IRQF_NO_SUSPEND | IRQF_ONESHOT,
|
||||
dev_name(&pdev->dev), priv);
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
pm_suspend_ignore_children(&pdev->dev, true);
|
||||
pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
|
||||
pm_runtime_use_autosuspend(priv->dev);
|
||||
pm_runtime_set_active(priv->dev);
|
||||
pm_runtime_enable(priv->dev);
|
||||
|
||||
ret = i2c_add_adapter(&priv->adap);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to add bus to i2c core\n");
|
||||
goto err_runtime;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
err_runtime:
|
||||
pm_runtime_disable(priv->dev);
|
||||
pm_runtime_set_suspended(priv->dev);
|
||||
err_clk:
|
||||
clk_disable_unprepare(priv->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hix5hd2_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
i2c_del_adapter(&priv->adap);
|
||||
pm_runtime_disable(priv->dev);
|
||||
pm_runtime_set_suspended(priv->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int hix5hd2_i2c_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hix5hd2_i2c_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
clk_prepare_enable(priv->clk);
|
||||
hix5hd2_i2c_init(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
|
||||
SET_PM_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
|
||||
hix5hd2_i2c_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
static const struct of_device_id hix5hd2_i2c_match[] = {
|
||||
{ .compatible = "hisilicon,hix5hd2-i2c" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
|
||||
|
||||
static struct platform_driver hix5hd2_i2c_driver = {
|
||||
.probe = hix5hd2_i2c_probe,
|
||||
.remove = hix5hd2_i2c_remove,
|
||||
.driver = {
|
||||
.name = "hix5hd2-i2c",
|
||||
.pm = &hix5hd2_i2c_pm_ops,
|
||||
.of_match_table = hix5hd2_i2c_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(hix5hd2_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
|
||||
MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:i2c-hix5hd2");
|
Loading…
Reference in a new issue