MLK-18869 - [i.MX8MM/Hantro]: Integrate 20180710 release
Implement different sync method, replace previous signal with ioctl Related functions were added (cherry-pick from : adc4bc267e5c3a33ca802de83e2693638a7be8e8) Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>pull/10/head
Zhou Peng
Jason Liu
parent
1e126efb6f
commit
1708063649
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@ -1,7 +1,7 @@
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/*
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* Encoder device driver (kernel module)
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*
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* Copyright (c) 2013-2017, VeriSilicon Inc.
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* Copyright (c) 2013-2018, VeriSilicon Inc.
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* Copyright (C) 2012 Google Finland Oy.
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*
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* This program is free software; you can redistribute it and/or
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@ -46,9 +46,9 @@
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#include <linux/sched.h>
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/* needed for virt_to_phys() */
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#include <asm/io.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <asm/uaccess.h>
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#include <linux/uaccess.h>
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#include <linux/ioport.h>
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#include <asm/irq.h>
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@ -98,7 +98,7 @@ MODULE_DESCRIPTION("Hantro 6280/7280/8270/8290/H1 Encoder driver");
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/* these could be module params in the future */
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#define ENC_IO_BASE INTEGRATOR_LOGIC_MODULE0_BASE
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#define ENC_IO_SIZE (300 * 4) /* bytes */
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#define ENC_IO_SIZE (500 * 4) /* bytes */
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#define ENC_HW_ID1 0x62800000
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#define ENC_HW_ID2 0x72800000
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@ -108,9 +108,16 @@ MODULE_DESCRIPTION("Hantro 6280/7280/8270/8290/H1 Encoder driver");
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#define HX280ENC_BUF_SIZE 0
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unsigned long base_port = INTEGRATOR_LOGIC_MODULE0_BASE;
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static unsigned long base_port = INTEGRATOR_LOGIC_MODULE0_BASE;
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static int irq = VP_PB_INT_LT;
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/* for critical data access */
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static DEFINE_SPINLOCK(owner_lock);
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/* for irq wait */
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static DECLARE_WAIT_QUEUE_HEAD(enc_wait_queue);
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/* for reserve hw */
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static DECLARE_WAIT_QUEUE_HEAD(enc_hw_queue);
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/* module_param(name, type, perm) */
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module_param(base_port, ulong, 0644);
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module_param(irq, int, 0644);
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@ -120,12 +127,17 @@ static int hx280enc_major;
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/* here's all the must remember stuff */
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typedef struct {
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char *buffer;
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unsigned int buffsize;
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u32 hw_id; //hw id to indicate project
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u32 is_valid; //indicate this core is hantro's core or not
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u32 is_reserved; //indicate this core is occupied by user or not
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int pid; //indicate which process is occupying the core
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u32 irq_received; //indicate this core receives irq
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u32 irq_status;
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int irq;
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unsigned long iobaseaddr;
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unsigned int iosize;
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volatile u8 *hwregs;
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unsigned int irq;
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struct fasync_struct *async_queue;
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} hx280enc_t;
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@ -141,55 +153,7 @@ static void dump_regs(unsigned long data);
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#endif
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/* IRQ handler */
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
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static irqreturn_t hx280enc_isr(int irq, void *dev_id, struct pt_regs *regs);
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#else
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static irqreturn_t hx280enc_isr(int irq, void *dev_id);
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#endif
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#ifdef VSI
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/* VM operations */
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 28))
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static struct page *hx280enc_vm_nopage(struct vm_area_struct *vma,
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unsigned long address, int *type)
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{
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PDEBUG("hx280enc_vm_nopage: problem with mem access\n");
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return NOPAGE_SIGBUS; /* send a SIGBUS */
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}
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#elif(LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0))
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static int hx280enc_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
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{
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PDEBUG("hx280enc_vm_fault: problem with mem access\n");
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return VM_FAULT_SIGBUS; /* send a SIGBUS */
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}
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#else
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static int hx280enc_vm_fault(struct vm_fault *vmf)
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{
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PDEBUG("hx280enc_vm_fault: problem with mem access\n");
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return VM_FAULT_SIGBUS; /* send a SIGBUS */
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}
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#endif
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static void hx280enc_vm_open(struct vm_area_struct *vma)
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{
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PDEBUG("hx280enc_vm_open:\n");
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}
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static void hx280enc_vm_close(struct vm_area_struct *vma)
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{
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PDEBUG("hx280enc_vm_close:\n");
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}
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static struct vm_operations_struct hx280enc_vm_ops = {
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open:hx280enc_vm_open,
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close:hx280enc_vm_close,
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 28))
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nopage:hx280enc_vm_nopage,
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#else
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fault:hx280enc_vm_fault,
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#endif
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};
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#endif
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#ifndef VSI
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static int hantro_h1_clk_enable(struct device *dev)
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@ -265,6 +229,98 @@ static int hx280enc_mmap(struct file *filp, struct vm_area_struct *vm)
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#endif
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}
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static int CheckEncIrq(hx280enc_t *dev)
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{
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unsigned long flags;
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int rdy = 0;
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spin_lock_irqsave(&owner_lock, flags);
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if (dev->irq_received) {
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/* reset the wait condition(s) */
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PDEBUG("check irq ready\n");
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dev->irq_received = 0;
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rdy = 1;
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}
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spin_unlock_irqrestore(&owner_lock, flags);
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//printk("rdy=%d\n",rdy);
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return rdy;
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}
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unsigned int WaitEncReady(hx280enc_t *dev)
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{
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PDEBUG("WaitEncReady\n");
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if (wait_event_interruptible(enc_wait_queue, CheckEncIrq(dev))) {
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PDEBUG("ENC wait_event_interruptible interrupted\n");
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return -ERESTARTSYS;
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}
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return 0;
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}
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int CheckCoreOccupation(hx280enc_t *dev)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&owner_lock, flags);
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if (!dev->is_reserved) {
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dev->is_reserved = 1;
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dev->pid = current->pid;
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ret = 1;
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PDEBUG("CheckCoreOccupation pid=%d\n", dev->pid);
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}
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spin_unlock_irqrestore(&owner_lock, flags);
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return ret;
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}
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int GetWorkableCore(hx280enc_t *dev)
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{
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int ret = 0;
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PDEBUG("GetWorkableCore\n");
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if (dev->is_valid && CheckCoreOccupation(dev))
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ret = 1;
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return ret;
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}
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long ReserveEncoder(hx280enc_t *dev)
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{
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/* lock a core that has specified core id*/
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if (wait_event_interruptible(enc_hw_queue, GetWorkableCore(dev) != 0))
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return -ERESTARTSYS;
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return 0;
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}
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void ReleaseEncoder(hx280enc_t *dev)
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{
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unsigned long flags;
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PDEBUG("ReleaseEncoder\n");
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spin_lock_irqsave(&owner_lock, flags);
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PDEBUG("relase reseve by pid=%d with current->pid=%d\n", dev->pid, current->pid);
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if (dev->is_reserved && dev->pid == current->pid) {
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dev->pid = -1;
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dev->is_reserved = 0;
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}
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dev->irq_received = 0;
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dev->irq_status = 0;
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spin_unlock_irqrestore(&owner_lock, flags);
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wake_up_interruptible_all(&enc_hw_queue);
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}
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static long hx280enc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
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{
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int err = 0;
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@ -299,6 +355,23 @@ static long hx280enc_ioctl(struct file *filp, unsigned int cmd, unsigned long ar
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case HX280ENC_IOCGHWIOSIZE:
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__put_user(hx280enc_data.iosize, (unsigned int *) arg);
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break;
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case HX280ENC_IOCH_ENC_RESERVE: {
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int ret;
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PDEBUG("Reserve ENC Cores\n");
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ret = ReserveEncoder(&hx280enc_data);
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return ret;
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}
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case HX280ENC_IOCH_ENC_RELEASE:
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PDEBUG("Release ENC Core\n");
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ReleaseEncoder(&hx280enc_data);
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break;
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case HX280ENC_IOCG_CORE_WAIT: {
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int ret;
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ret = WaitEncReady(&hx280enc_data);
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return ret;
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}
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}
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return 0;
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}
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@ -319,42 +392,42 @@ static int hx280enc_open(struct inode *inode, struct file *filp)
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return result;
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}
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static int hx280enc_fasync(int fd, struct file *filp, int mode)
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{
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hx280enc_t *dev = (hx280enc_t *) filp->private_data;
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PDEBUG("fasync called\n");
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return fasync_helper(fd, filp, mode, &dev->async_queue);
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}
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static int hx280enc_release(struct inode *inode, struct file *filp)
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{
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#ifdef HX280ENC_DEBUG
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hx280enc_t *dev = (hx280enc_t *) filp->private_data;
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unsigned long flags;
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#ifdef HX280ENC_DEBUG
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dump_regs((unsigned long) dev); /* dump the regs */
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#endif
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/* remove this filp from the asynchronusly notified filp's */
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hx280enc_fasync(-1, filp, 0);
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PDEBUG("dev closed\n");
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spin_lock_irqsave(&owner_lock, flags);
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if (dev->is_reserved == 1 && dev->pid == current->pid) {
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dev->pid = -1;
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dev->is_reserved = 0;
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dev->irq_received = 0;
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dev->irq_status = 0;
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PDEBUG("release reserved core\n");
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}
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spin_unlock_irqrestore(&owner_lock, flags);
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wake_up_interruptible_all(&enc_hw_queue);
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#ifndef VSI
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pm_runtime_put_sync(hantro_h1_dev);
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hantro_h1_clk_disable(hantro_h1_dev);
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#endif
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PDEBUG("dev closed\n");
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return 0;
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}
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/* VFS methods */
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static struct file_operations hx280enc_fops = {
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mmap:hx280enc_mmap,
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open:hx280enc_open,
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release:hx280enc_release,
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unlocked_ioctl:hx280enc_ioctl,
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fasync:hx280enc_fasync,
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.owner = THIS_MODULE,
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.open = hx280enc_open,
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.release = hx280enc_release,
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.unlocked_ioctl = hx280enc_ioctl,
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.fasync = NULL,
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.mmap = hx280enc_mmap,
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};
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#ifndef VSI
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@ -393,7 +466,8 @@ static int __init hx280enc_init(void)
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
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SA_INTERRUPT | SA_SHIRQ,
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#else
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IRQF_DISABLED | IRQF_SHARED,
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//IRQF_DISABLED | IRQF_SHARED,
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IRQF_SHARED,
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#endif
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"hx280enc", (void *) &hx280enc_data);
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if (result == -EINVAL) {
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@ -457,7 +531,7 @@ static int ReserveIO(void)
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}
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hwid = readl(hx280enc_data.hwregs);
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#if 1
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/* check for encoder HW ID */
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if ((((hwid >> 16) & 0xFFFF) != ((ENC_HW_ID1 >> 16) & 0xFFFF)) &&
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(((hwid >> 16) & 0xFFFF) != ((ENC_HW_ID2 >> 16) & 0xFFFF)) &&
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@ -471,33 +545,40 @@ static int ReserveIO(void)
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ReleaseIO();
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return -EBUSY;
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}
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#endif
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hx280enc_data.hw_id = hwid;
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hx280enc_data.is_valid = 1;
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PDEBUG(KERN_INFO "hx280enc: HW at base <0x%08lx> with ID <0x%08lx>\n", hx280enc_data.iobaseaddr, hwid);
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return 0;
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}
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static void ReleaseIO(void)
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{
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if (hx280enc_data.is_valid == 0)
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return;
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if (hx280enc_data.hwregs)
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iounmap((void *) hx280enc_data.hwregs);
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release_mem_region(hx280enc_data.iobaseaddr, hx280enc_data.iosize);
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}
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
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irqreturn_t hx280enc_isr(int irq, void *dev_id, struct pt_regs *regs)
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#else
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irqreturn_t hx280enc_isr(int irq, void *dev_id)
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#endif
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{
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hx280enc_t *dev = (hx280enc_t *) dev_id;
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u32 irq_status;
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unsigned long flags;
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u32 is_write1_clr;
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spin_lock_irqsave(&owner_lock, flags);
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if (!dev->is_reserved) {
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spin_unlock_irqrestore(&owner_lock, flags);
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return IRQ_HANDLED;
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}
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spin_unlock_irqrestore(&owner_lock, flags);
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irq_status = readl(dev->hwregs + 0x04);
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/* BASE_HWFuse2 = 0x4a0; HWCFGIrqClearSupport = 0x00800000 */
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is_write1_clr = (readl(dev->hwregs + 0x4a0) & 0x00800000);
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if (irq_status & 0x01) {
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/* clear enc IRQ and slice ready interrupt bit */
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if (is_write1_clr)
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@ -513,13 +594,12 @@ irqreturn_t hx280enc_isr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/* All other interrupts will be signaled to EWL. */
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if (dev->async_queue)
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kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
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else {
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PDEBUG(KERN_WARNING
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"hx280enc: IRQ received w/o anybody waiting for it!\n");
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}
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spin_lock_irqsave(&owner_lock, flags);
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dev->irq_received = 1;
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dev->irq_status = irq_status & (~0x01);
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spin_unlock_irqrestore(&owner_lock, flags);
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wake_up_interruptible_all(&enc_wait_queue);
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PDEBUG("IRQ handled!\n");
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return IRQ_HANDLED;
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@ -533,11 +613,13 @@ static void ResetAsic(hx280enc_t *dev)
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{
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int i;
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if (dev->is_valid == 0)
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return;
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writel(0, dev->hwregs + 0x38);
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for (i = 4; i < dev->iosize; i += 4)
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writel(0, dev->hwregs + i);
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}
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#ifdef HX280ENC_DEBUG
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@ -68,7 +68,12 @@
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#define HX280ENC_IOCXVIRT2BUS _IOWR(HX280ENC_IOC_MAGIC, 7, unsigned long *)
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#define HX280ENC_IOCHARDRESET _IO(HX280ENC_IOC_MAGIC, 8) /* debugging tool */
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#define HX280ENC_IOCGSRAMOFFSET _IOR(HX280ENC_IOC_MAGIC, 9, unsigned long *)
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#define HX280ENC_IOCGSRAMEIOSIZE _IOR(HX280ENC_IOC_MAGIC, 10, unsigned int *)
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#define HX280ENC_IOC_MAXNR 8
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#define HX280ENC_IOCH_ENC_RESERVE _IOR(HX280ENC_IOC_MAGIC, 11, unsigned int *)
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#define HX280ENC_IOCH_ENC_RELEASE _IOR(HX280ENC_IOC_MAGIC, 12, unsigned int *)
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#define HX280ENC_IOCG_CORE_WAIT _IOR(HX280ENC_IOC_MAGIC, 13, unsigned int *)
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#define HX280ENC_IOC_MAXNR 30
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#endif /* !_UAPI_HX280ENC_H_ */
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@ -68,7 +68,12 @@
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#define HX280ENC_IOCXVIRT2BUS _IOWR(HX280ENC_IOC_MAGIC, 7, unsigned long *)
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#define HX280ENC_IOCHARDRESET _IO(HX280ENC_IOC_MAGIC, 8) /* debugging tool */
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#define HX280ENC_IOCGSRAMOFFSET _IOR(HX280ENC_IOC_MAGIC, 9, unsigned long *)
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#define HX280ENC_IOCGSRAMEIOSIZE _IOR(HX280ENC_IOC_MAGIC, 10, unsigned int *)
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#define HX280ENC_IOC_MAXNR 8
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#define HX280ENC_IOCH_ENC_RESERVE _IOR(HX280ENC_IOC_MAGIC, 11, unsigned int *)
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#define HX280ENC_IOCH_ENC_RELEASE _IOR(HX280ENC_IOC_MAGIC, 12, unsigned int *)
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#define HX280ENC_IOCG_CORE_WAIT _IOR(HX280ENC_IOC_MAGIC, 13, unsigned int *)
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#define HX280ENC_IOC_MAXNR 30
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#endif /* !_UAPI_HX280ENC_H_ */
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