drm/i915: support 64K pages for the 48b PPGTT
Support inserting 64K pages into the 48b PPGTT. v2: check for 64K scratch v3: we should only have to re-adjust maybe_64K at every sg interval Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-15-matthew.auld@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-14-chris@chris-wilson.co.uk
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@ -1069,6 +1069,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
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struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
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struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
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struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
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struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
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unsigned int page_size;
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unsigned int page_size;
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bool maybe_64K = false;
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gen8_pte_t encode = pte_encode;
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gen8_pte_t encode = pte_encode;
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gen8_pte_t *vaddr;
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gen8_pte_t *vaddr;
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u16 index, max;
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u16 index, max;
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@ -1090,6 +1091,13 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
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max = GEN8_PTES;
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max = GEN8_PTES;
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page_size = I915_GTT_PAGE_SIZE;
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page_size = I915_GTT_PAGE_SIZE;
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if (!index &&
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vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
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IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
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(IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
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rem >= (max - index) << PAGE_SHIFT))
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maybe_64K = true;
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vaddr = kmap_atomic_px(pt);
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vaddr = kmap_atomic_px(pt);
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}
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}
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@ -1109,12 +1117,35 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
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iter->dma = sg_dma_address(iter->sg);
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iter->dma = sg_dma_address(iter->sg);
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iter->max = iter->dma + rem;
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iter->max = iter->dma + rem;
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if (maybe_64K && index < max &&
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!(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
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(IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
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rem >= (max - index) << PAGE_SHIFT)))
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maybe_64K = false;
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if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
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if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
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break;
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break;
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}
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}
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} while (rem >= page_size && index < max);
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} while (rem >= page_size && index < max);
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kunmap_atomic(vaddr);
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kunmap_atomic(vaddr);
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/*
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* Is it safe to mark the 2M block as 64K? -- Either we have
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* filled whole page-table with 64K entries, or filled part of
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* it and have reached the end of the sg table and we have
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* enough padding.
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*/
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if (maybe_64K &&
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(index == max ||
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(i915_vm_has_scratch_64K(vma->vm) &&
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!iter->sg && IS_ALIGNED(vma->node.start +
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vma->node.size,
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I915_GTT_PAGE_SIZE_2M)))) {
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vaddr = kmap_atomic_px(pd);
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vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
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kunmap_atomic(vaddr);
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}
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} while (iter->sg);
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} while (iter->sg);
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}
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}
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@ -154,6 +154,7 @@ typedef u64 gen8_ppgtt_pml4e_t;
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#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
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#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
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#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
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#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
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#define GEN8_PDE_IPS_64K BIT(11)
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#define GEN8_PDE_PS_2M BIT(7)
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#define GEN8_PDE_PS_2M BIT(7)
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struct sg_table;
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struct sg_table;
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@ -352,6 +353,12 @@ i915_vm_is_48bit(const struct i915_address_space *vm)
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return (vm->total - 1) >> 32;
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return (vm->total - 1) >> 32;
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}
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}
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static inline bool
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i915_vm_has_scratch_64K(struct i915_address_space *vm)
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{
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return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K);
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}
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/* The Graphics Translation Table is the way in which GEN hardware translates a
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/* The Graphics Translation Table is the way in which GEN hardware translates a
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* Graphics Virtual Address into a Physical Address. In addition to the normal
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* Graphics Virtual Address into a Physical Address. In addition to the normal
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* collateral associated with any va->pa translations GEN hardware also has a
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* collateral associated with any va->pa translations GEN hardware also has a
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