Merge branches 'x86-apic-for-linus', 'x86-asm-for-linus' and 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, apic: Print verbose error interrupt reason on apic=debug * 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: Demacro CONFIG_PARAVIRT cpu accessors * 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: Fix mrst sparse complaints x86: Fix spelling error in the memcpy() source code comment x86, mpparse: Remove unnecessary variable
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commit
17b141803c
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@ -303,24 +303,81 @@ static inline void native_wbinvd(void)
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define read_cr0() (native_read_cr0())
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#define write_cr0(x) (native_write_cr0(x))
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#define read_cr2() (native_read_cr2())
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#define write_cr2(x) (native_write_cr2(x))
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#define read_cr3() (native_read_cr3())
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#define write_cr3(x) (native_write_cr3(x))
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#define read_cr4() (native_read_cr4())
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#define read_cr4_safe() (native_read_cr4_safe())
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#define write_cr4(x) (native_write_cr4(x))
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#define wbinvd() (native_wbinvd())
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static inline unsigned long read_cr0(void)
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{
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return native_read_cr0();
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}
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static inline void write_cr0(unsigned long x)
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{
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native_write_cr0(x);
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}
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static inline unsigned long read_cr2(void)
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{
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return native_read_cr2();
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}
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static inline void write_cr2(unsigned long x)
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{
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native_write_cr2(x);
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}
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static inline unsigned long read_cr3(void)
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{
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return native_read_cr3();
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}
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static inline void write_cr3(unsigned long x)
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{
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native_write_cr3(x);
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}
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static inline unsigned long read_cr4(void)
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{
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return native_read_cr4();
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}
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static inline unsigned long read_cr4_safe(void)
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{
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return native_read_cr4_safe();
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}
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static inline void write_cr4(unsigned long x)
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{
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native_write_cr4(x);
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}
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static inline void wbinvd(void)
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{
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native_wbinvd();
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}
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#ifdef CONFIG_X86_64
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#define read_cr8() (native_read_cr8())
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#define write_cr8(x) (native_write_cr8(x))
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#define load_gs_index native_load_gs_index
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static inline unsigned long read_cr8(void)
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{
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return native_read_cr8();
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}
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static inline void write_cr8(unsigned long x)
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{
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native_write_cr8(x);
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}
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static inline void load_gs_index(unsigned selector)
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{
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native_load_gs_index(selector);
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}
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#endif
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/* Clear the 'TS' bit */
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#define clts() (native_clts())
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static inline void clts(void)
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{
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native_clts();
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}
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#endif/* CONFIG_PARAVIRT */
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@ -1812,30 +1812,41 @@ void smp_spurious_interrupt(struct pt_regs *regs)
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*/
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void smp_error_interrupt(struct pt_regs *regs)
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{
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u32 v, v1;
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u32 v0, v1;
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u32 i = 0;
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static const char * const error_interrupt_reason[] = {
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"Send CS error", /* APIC Error Bit 0 */
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"Receive CS error", /* APIC Error Bit 1 */
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"Send accept error", /* APIC Error Bit 2 */
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"Receive accept error", /* APIC Error Bit 3 */
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"Redirectable IPI", /* APIC Error Bit 4 */
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"Send illegal vector", /* APIC Error Bit 5 */
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"Received illegal vector", /* APIC Error Bit 6 */
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"Illegal register address", /* APIC Error Bit 7 */
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};
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exit_idle();
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irq_enter();
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/* First tickle the hardware, only then report what went on. -- REW */
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v = apic_read(APIC_ESR);
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v0 = apic_read(APIC_ESR);
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apic_write(APIC_ESR, 0);
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v1 = apic_read(APIC_ESR);
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ack_APIC_irq();
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atomic_inc(&irq_err_count);
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/*
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* Here is what the APIC error bits mean:
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* 0: Send CS error
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* 1: Receive CS error
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* 2: Send accept error
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* 3: Receive accept error
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* 4: Reserved
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* 5: Send illegal vector
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* 6: Received illegal vector
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* 7: Illegal register address
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*/
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pr_debug("APIC error on CPU%d: %02x(%02x)\n",
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smp_processor_id(), v , v1);
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apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
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smp_processor_id(), v0 , v1);
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v1 = v1 & 0xff;
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while (v1) {
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if (v1 & 0x1)
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apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
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i++;
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v1 >>= 1;
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};
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apic_printk(APIC_DEBUG, KERN_CONT "\n");
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irq_exit();
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}
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@ -718,14 +718,12 @@ static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
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static int
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check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count)
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{
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int ret = 0;
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if (!mpc_new_phys || count <= mpc_new_length) {
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WARN(1, "update_mptable: No spare slots (length: %x)\n", count);
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return -1;
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}
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return ret;
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return 0;
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}
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#else /* CONFIG_X86_IO_APIC */
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static
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@ -67,7 +67,7 @@ ENTRY(memcpy)
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jb .Lhandle_tail
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/*
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* We check whether memory false dependece could occur,
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* We check whether memory false dependence could occur,
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* then jump to corresponding copy mode.
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*/
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cmp %dil, %sil
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@ -194,7 +194,7 @@ static unsigned long __init mrst_calibrate_tsc(void)
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return 0;
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}
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void __init mrst_time_init(void)
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static void __init mrst_time_init(void)
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{
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sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
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switch (mrst_timer_options) {
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@ -216,7 +216,7 @@ void __init mrst_time_init(void)
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apbt_time_init();
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}
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void __cpuinit mrst_arch_setup(void)
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static void __cpuinit mrst_arch_setup(void)
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{
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if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
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__mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
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