clk: sunxi-ng: r40: export a regmap to access the GMAC register
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in the syscon part, in the CCU of R40 SoC. Export a regmap of the CCU. Read access is not restricted to all registers, but only the GMAC register is allowed to be written. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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@ -1251,9 +1251,37 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
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.bypass_index = 1, /* index of 24 MHz oscillator */
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};
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/*
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* Add a regmap for the GMAC driver (dwmac-sun8i) to access the
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* GMAC configuration register.
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* Only this register is allowed to be written, in order to
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* prevent overriding critical clock configuration.
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*/
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#define SUN8I_R40_GMAC_CFG_REG 0x164
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static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
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unsigned int reg)
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{
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if (reg == SUN8I_R40_GMAC_CFG_REG)
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return true;
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return false;
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}
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static struct regmap_config sun8i_r40_ccu_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x320, /* PLL_LOCK_CTRL_REG */
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/* other devices have no business accessing other registers */
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.readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
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.writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
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};
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static int sun8i_r40_ccu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct regmap *regmap;
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void __iomem *reg;
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u32 val;
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int ret;
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@ -1278,6 +1306,11 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
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val &= ~GENMASK(25, 20);
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writel(val, reg + SUN8I_R40_USB_CLK_REG);
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regmap = devm_regmap_init_mmio(&pdev->dev, reg,
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&sun8i_r40_ccu_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
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if (ret)
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return ret;
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