MLK-18247 clk: imx: add more pll frequency setting in clock rate table
Add 1GHz, 800MHz, 700MHz, 600MHz pll clock rate setting in the pll clock calculation table of imx8mm. These frequency point are needed by VPU and GPU driver. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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@ -64,10 +64,14 @@ enum {
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}
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static const struct imx_int_pll_rate_table imx8mm_intpll_tbl[] = {
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PLL_1416X_RATE(1800000000U, 0xe1, 3, 0),
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PLL_1416X_RATE(1600000000U, 0xc8, 3, 0),
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PLL_1416X_RATE(1200000000U, 0x12c, 3, 1),
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PLL_1416X_RATE(750000000U, 0xfa, 2, 2),
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PLL_1416X_RATE(1800000000U, 225, 3, 0),
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PLL_1416X_RATE(1600000000U, 200, 3, 0),
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PLL_1416X_RATE(1200000000U, 300, 3, 1),
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PLL_1416X_RATE(1000000000U, 250, 3, 1),
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PLL_1416X_RATE(800000000U, 200, 3, 1),
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PLL_1416X_RATE(750000000U, 250, 2, 2),
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PLL_1416X_RATE(700000000U, 350, 3, 2),
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PLL_1416X_RATE(600000000U, 300, 3, 2),
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};
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static const struct imx_int_pll_rate_table imx8mm_audiopll_tbl[] = {
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@ -76,11 +80,11 @@ static const struct imx_int_pll_rate_table imx8mm_audiopll_tbl[] = {
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};
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static const struct imx_int_pll_rate_table imx8mm_videopll_tbl[] = {
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PLL_1443X_RATE(650000000U, 0x145, 3, 2, 0),
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PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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};
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static const struct imx_int_pll_rate_table imx8mm_drampll_tbl[] = {
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PLL_1443X_RATE(650000000U, 0x145, 3, 2, 0),
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PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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};
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static struct imx_int_pll_clk imx8mm_audio_pll __initdata = {
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