MLK-20053 arm64: dts: Add DTS for iMX8MM DDR3L validation board
Add the DTS file for iMX8MM DDR3L validation board to support basic modules: I2C, UART, ENET RMII, SD, NAND and USB. Bus freq is disabled since we currently don't support it for DDR3L. This board has a FPGA which owns the ENET PHY RESET and WDOG_B, so The ENET won't work due to PHY RESET is hold high at default. And system reboot won't work neither. Signed-off-by: Ye Li <ye.li@nxp.com>pull/10/head
parent
c441ced3f1
commit
18cdeadfe1
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@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \
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fsl-imx8mm-evk-m4.dtb \
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fsl-imx8mm-evk-ak5558.dtb \
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fsl-imx8mm-evk-audio-tdm.dtb \
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fsl-imx8mm-ddr3l-val.dtb \
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fsl-imx8mm-ddr4-evk.dtb \
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fsl-imx8mm-ddr4-val.dtb \
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fsl-imx8mm-evk-rm67191.dtb \
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@ -0,0 +1,386 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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/dts-v1/;
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#include "fsl-imx8mm.dtsi"
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/ {
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model = "FSL i.MX8MM DDR3L Validation board";
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compatible = "fsl,imx8mm-val", "fsl,imx8mm";
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chosen {
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bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
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stdout-path = &uart2;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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busfreq {
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status = "disabled";
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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imx8mm-val {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
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MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
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MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
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MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
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MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
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MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
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MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
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MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
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MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
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MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
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MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
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MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
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MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
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MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
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MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
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MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
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MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
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>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: bd71837@4b {
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reg = <0x4b>;
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compatible = "rohm,bd71837";
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gpo {
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rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
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};
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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bd71837,pmic-buck2-uses-i2c-dvs;
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bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
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buck1_reg: regulator@0 {
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reg = <0>;
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regulator-compatible = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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buck2_reg: regulator@1 {
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reg = <1>;
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regulator-compatible = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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buck3_reg: regulator@2 {
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reg = <2>;
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regulator-compatible = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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};
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buck4_reg: regulator@3 {
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reg = <3>;
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regulator-compatible = "buck4";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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};
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buck5_reg: regulator@4 {
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reg = <4>;
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regulator-compatible = "buck5";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6_reg: regulator@5 {
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reg = <5>;
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regulator-compatible = "buck6";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck7_reg: regulator@6 {
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reg = <6>;
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regulator-compatible = "buck7";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck8_reg: regulator@7 {
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reg = <7>;
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regulator-compatible = "buck8";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: regulator@8 {
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reg = <8>;
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regulator-compatible = "ldo1";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: regulator@9 {
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reg = <9>;
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regulator-compatible = "ldo2";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: regulator@10 {
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reg = <10>;
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regulator-compatible = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: regulator@11 {
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reg = <11>;
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regulator-compatible = "ldo4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5_reg: regulator@12 {
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reg = <12>;
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regulator-compatible = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo6_reg: regulator@13 {
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reg = <13>;
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regulator-compatible = "ldo6";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo7_reg: regulator@14 {
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reg = <14>;
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regulator-compatible = "ldo7";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&mu {
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status = "okay";
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};
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&rpmsg{
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/*
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* 64K for one rpmsg instance:
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* --0xb8000000~0xb800ffff: pingpong
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*/
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vdev-nums = <1>;
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reg = <0x0 0xb8000000 0x0 0x10000>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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};
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&uart2 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "host";
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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non-removable;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "okay";
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nand-on-flash-bbt;
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};
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&A53_0 {
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arm-supply = <&buck2_reg>;
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};
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