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clk: mediatek: Fix calculation of PLL rate settings

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Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
James Liao 2015-07-10 16:39:33 +08:00 committed by Stephen Boyd
parent b3be457e58
commit 196de71a9d
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/mediatek/clk-pll.c
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@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
if (freq > pll->data->fmax)
freq = pll->data->fmax;
for (val = 0; val < 4; val++) {
for (val = 0; val < 5; val++) {
*postdiv = 1 << val;
if (freq * *postdiv >= fmin)
if ((u64)freq * *postdiv >= fmin)
break;
}