sh: se7343: Move CPLD IRQs to irqdomain and generic irq chip.
Follows the se7722 change, see there for more information. Signed-off-by: Paul Mundt <lethal@linux-sh.org>wifi-calibration
Paul Mundt
parent
5df38b9b76
commit
197b58e665
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@ -81,6 +81,8 @@ config SH_7780_SOLUTION_ENGINE
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config SH_7343_SOLUTION_ENGINE
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bool "SolutionEngine7343"
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select SOLUTION_ENGINE
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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depends on CPU_SUBTYPE_SH7343
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help
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Select 7343 SolutionEngine if configuring for a Hitachi
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@ -1,54 +1,109 @@
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/*
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* linux/arch/sh/boards/se/7343/irq.c
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* Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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* Copyright (C) 2012 Paul Mundt
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*
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* Based on linux/arch/sh/boards/se/7722/irq.c
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* Based on linux/arch/sh/boards/se/7343/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "SE7343-FPGA"
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#define pr_fmt(fmt) DRV_NAME ": " fmt
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#define irq_reg_readl ioread16
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#define irq_reg_writel iowrite16
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <asm/sizes.h>
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#include <mach-se/mach/se7343.h>
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unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
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#define PA_CPLD_BASE_ADDR 0x11400000
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#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */
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#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */
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static void disable_se7343_irq(struct irq_data *data)
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{
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unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
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__raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
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}
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static void enable_se7343_irq(struct irq_data *data)
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{
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unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
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__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
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}
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static struct irq_chip se7343_irq_chip __read_mostly = {
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.name = "SE7343-FPGA",
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.irq_mask = disable_se7343_irq,
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.irq_unmask = enable_se7343_irq,
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};
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static void __iomem *se7343_irq_regs;
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struct irq_domain *se7343_irq_domain;
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static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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unsigned short intv = __raw_readw(PA_CPLD_ST);
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unsigned int ext_irq = 0;
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struct irq_data *data = irq_get_irq_data(irq);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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unsigned long mask;
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int bit;
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intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
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chip->irq_mask_ack(data);
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for (; intv; intv >>= 1, ext_irq++) {
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if (!(intv & 1))
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continue;
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mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
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generic_handle_irq(se7343_fpga_irq[ext_irq]);
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for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
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generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
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chip->irq_unmask(data);
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}
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static void __init se7343_domain_init(void)
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{
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int i;
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se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
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&irq_domain_simple_ops, NULL);
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if (unlikely(!se7343_irq_domain)) {
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printk("Failed to get IRQ domain\n");
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return;
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}
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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int irq = irq_create_mapping(se7343_irq_domain, i);
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if (unlikely(irq == 0)) {
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printk("Failed to allocate IRQ %d\n", i);
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return;
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}
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}
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}
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static void __init se7343_gc_init(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int irq_base;
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irq_base = irq_linear_revmap(se7343_irq_domain, 0);
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gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
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handle_level_irq);
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if (unlikely(!gc))
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return;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->regs.mask = PA_CPLD_IMSK_REG;
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irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
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IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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/*
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@ -56,31 +111,19 @@ static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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*/
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void __init init_7343se_IRQ(void)
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{
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int i, irq;
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__raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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irq = create_irq();
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if (irq < 0)
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return;
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se7343_fpga_irq[i] = irq;
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irq_set_chip_and_handler_name(se7343_fpga_irq[i],
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&se7343_irq_chip,
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handle_level_irq,
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"level");
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irq_set_chip_data(se7343_fpga_irq[i], (void *)i);
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se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
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if (unlikely(!se7343_irq_regs)) {
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pr_err("Failed to remap CPLD\n");
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return;
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}
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irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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/*
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* All FPGA IRQs disabled by default
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*/
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iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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se7343_domain_init();
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se7343_gc_init();
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}
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@ -5,6 +5,7 @@
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#include <linux/serial_reg.h>
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#include <linux/usb/isp116x.h>
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#include <linux/delay.h>
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#include <linux/irqdomain.h>
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#include <asm/machvec.h>
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#include <mach-se/mach/se7343.h>
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#include <asm/heartbeat.h>
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@ -145,11 +146,12 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
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static int __init sh7343se_devices_setup(void)
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{
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/* Wire-up dynamic vectors */
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serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];
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serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];
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serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,
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SE7343_FPGA_IRQ_UARTA);
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serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,
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SE7343_FPGA_IRQ_UARTB);
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usb_resources[2].start = usb_resources[2].end =
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se7343_fpga_irq[SE7343_FPGA_IRQ_USB];
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irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);
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return platform_add_devices(sh7343se_platform_devices,
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ARRAY_SIZE(sh7343se_platform_devices));
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@ -49,9 +49,6 @@
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#define PA_LED 0xb0C00000 /* LED */
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#define LED_SHIFT 0
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#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
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#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
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#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
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#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
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/* Area 5 */
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#define PA_EXT5 0x14000000
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#define PA_EXT5_SIZE 0x04000000
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@ -134,8 +131,10 @@
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#define SE7343_FPGA_IRQ_NR 12
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struct irq_domain;
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/* arch/sh/boards/se/7343/irq.c */
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extern unsigned int se7343_fpga_irq[];
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extern struct irq_domain *se7343_irq_domain;
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void init_7343se_IRQ(void);
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