dmaengine: dw: add support of iDMA 32-bit hardware
iDMA 32-bit is Intel designed DMA controller that behaves like Synopsys Designware DMA. This patch adds a support of the new Intel hardware. Due to iDMA 32-bit has no autoconfiguration the platform code must provide a platform data to dw_dma_probe(). By default full FIFO (1024 bytes) is assigned to channel 0. Here we slice FIFO on equal parts between channels for iDMA 32-bit case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -138,16 +138,32 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
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dwc->descs_allocated--;
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}
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static void dwc_initialize(struct dw_dma_chan *dwc)
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static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
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{
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u32 cfghi = 0;
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u32 cfglo = 0;
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/* Set default burst alignment */
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cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
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/* Low 4 bits of the request lines */
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cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
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cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
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/* Request line extension (2 bits) */
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cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
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cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
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channel_writel(dwc, CFG_LO, cfglo);
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channel_writel(dwc, CFG_HI, cfghi);
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}
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static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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u32 cfghi = DWC_CFGH_FIFO_MODE;
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u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
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bool hs_polarity = dwc->dws.hs_polarity;
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if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
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return;
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cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
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cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
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@ -156,6 +172,19 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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channel_writel(dwc, CFG_LO, cfglo);
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channel_writel(dwc, CFG_HI, cfghi);
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}
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static void dwc_initialize(struct dw_dma_chan *dwc)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
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return;
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if (dw->pdata->is_idma32)
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dwc_initialize_chan_idma32(dwc);
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else
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dwc_initialize_chan_dw(dwc);
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/* Enable interrupts */
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channel_set_bit(dw, MASK.XFER, dwc->mask);
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@ -187,8 +216,13 @@ static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
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static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes,
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unsigned int width, size_t *len)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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u32 block;
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/* Always in bytes for iDMA 32-bit */
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if (dw->pdata->is_idma32)
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width = 0;
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if ((bytes >> width) > dwc->block_size) {
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block = dwc->block_size;
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*len = block << width;
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@ -202,6 +236,11 @@ static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes,
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static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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if (dw->pdata->is_idma32)
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return IDMA32C_CTLH_BLOCK_TS(block);
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return DWC_CTLH_BLOCK_TS(block) << width;
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}
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@ -915,14 +954,16 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dma_slave_config *sc = &dwc->dma_sconfig;
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struct dw_dma *dw = to_dw_dma(chan->device);
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/*
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* Fix sconfig's burst size according to dw_dmac. We need to convert
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* them as:
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* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
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*
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* NOTE: burst size 2 is not supported by DesignWare controller.
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* iDMA 32-bit supports it.
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*/
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u32 s = 2;
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u32 s = dw->pdata->is_idma32 ? 1 : 2;
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/* Check if chan will be configured for slave transfers */
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if (!is_slave_direction(sconfig->direction))
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@ -937,12 +978,19 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
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return 0;
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}
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static void dwc_chan_pause(struct dw_dma_chan *dwc)
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static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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unsigned int count = 20; /* timeout iterations */
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u32 cfglo;
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cfglo = channel_readl(dwc, CFG_LO);
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if (dw->pdata->is_idma32) {
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if (drain)
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cfglo |= IDMA32C_CFGL_CH_DRAIN;
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else
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cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
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}
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channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
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while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
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udelay(2);
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@ -956,7 +1004,7 @@ static int dwc_pause(struct dma_chan *chan)
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unsigned long flags;
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spin_lock_irqsave(&dwc->lock, flags);
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dwc_chan_pause(dwc);
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dwc_chan_pause(dwc, false);
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spin_unlock_irqrestore(&dwc->lock, flags);
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return 0;
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@ -998,6 +1046,8 @@ static int dwc_terminate_all(struct dma_chan *chan)
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clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
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dwc_chan_pause(dwc, true);
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dwc_chan_disable(dw, dwc);
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dwc_chan_resume(dwc);
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@ -1090,6 +1140,32 @@ static void dwc_issue_pending(struct dma_chan *chan)
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/*----------------------------------------------------------------------*/
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/*
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* Program FIFO size of channels.
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*
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* By default full FIFO (1024 bytes) is assigned to channel 0. Here we
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* slice FIFO on equal parts between channels.
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*/
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static void idma32_fifo_partition(struct dw_dma *dw)
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{
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u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
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IDMA32C_FP_UPDATE;
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u64 fifo_partition = 0;
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if (!dw->pdata->is_idma32)
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return;
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/* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
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fifo_partition |= value << 0;
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/* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
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fifo_partition |= value << 32;
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/* Program FIFO Partition registers - 128 bytes for each channel */
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idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
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idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
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}
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static void dw_dma_off(struct dw_dma *dw)
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{
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unsigned int i;
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@ -1509,7 +1585,12 @@ int dw_dma_probe(struct dw_dma_chip *chip)
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/* Force dma off, just in case */
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dw_dma_off(dw);
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idma32_fifo_partition(dw);
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/* Device and instance ID for IRQ and DMA pool */
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if (pdata->is_idma32)
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snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id);
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else
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snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id);
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/* Create a pool of consistent memory blocks for hardware descriptors */
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@ -1673,6 +1754,8 @@ int dw_dma_enable(struct dw_dma_chip *chip)
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{
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struct dw_dma *dw = chip->dw;
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idma32_fifo_partition(dw);
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dw_dma_on(dw);
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return 0;
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}
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@ -41,6 +41,7 @@ struct dw_dma_slave {
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* @is_private: The device channels should be marked as private and not for
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* by the general purpose DMA channel allocator.
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* @is_memcpy: The device channels do support memory-to-memory transfers.
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* @is_idma32: The type of the DMA controller is iDMA32
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* @chan_allocation_order: Allocate channels starting from 0 or 7
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* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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* @block_size: Maximum block size supported by the controller
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@ -53,6 +54,7 @@ struct dw_dma_platform_data {
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unsigned int nr_channels;
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bool is_private;
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bool is_memcpy;
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bool is_idma32;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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