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ARM: l2c: fix register naming

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We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess.  Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices.  Provide full auxiliary control register definitions.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-03-16 20:52:25 +00:00
parent a8875a092a
commit 1a5a954ce0
14 changed files with 118 additions and 95 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

73
arch/arm/include/asm/hardware/cache-l2x0.h
View file

@ -26,8 +26,8 @@
#define L2X0_CACHE_TYPE 0x004 #define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100 #define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104 #define L2X0_AUX_CTRL 0x104
#define L2X0_TAG_LATENCY_CTRL 0x108 #define L310_TAG_LATENCY_CTRL 0x108
#define L2X0_DATA_LATENCY_CTRL 0x10C #define L310_DATA_LATENCY_CTRL 0x10C
#define L2X0_EVENT_CNT_CTRL 0x200 #define L2X0_EVENT_CNT_CTRL 0x200
#define L2X0_EVENT_CNT1_CFG 0x204 #define L2X0_EVENT_CNT1_CFG 0x204
#define L2X0_EVENT_CNT0_CFG 0x208 #define L2X0_EVENT_CNT0_CFG 0x208
@ -54,16 +54,16 @@
#define L2X0_LOCKDOWN_WAY_D_BASE 0x900 #define L2X0_LOCKDOWN_WAY_D_BASE 0x900
#define L2X0_LOCKDOWN_WAY_I_BASE 0x904 #define L2X0_LOCKDOWN_WAY_I_BASE 0x904
#define L2X0_LOCKDOWN_STRIDE 0x08 #define L2X0_LOCKDOWN_STRIDE 0x08
#define L2X0_ADDR_FILTER_START 0xC00 #define L310_ADDR_FILTER_START 0xC00
#define L2X0_ADDR_FILTER_END 0xC04 #define L310_ADDR_FILTER_END 0xC04
#define L2X0_TEST_OPERATION 0xF00 #define L2X0_TEST_OPERATION 0xF00
#define L2X0_LINE_DATA 0xF10 #define L2X0_LINE_DATA 0xF10
#define L2X0_LINE_TAG 0xF30 #define L2X0_LINE_TAG 0xF30
#define L2X0_DEBUG_CTRL 0xF40 #define L2X0_DEBUG_CTRL 0xF40
#define L2X0_PREFETCH_CTRL 0xF60 #define L310_PREFETCH_CTRL 0xF60
#define L2X0_POWER_CTRL 0xF80 #define L310_POWER_CTRL 0xF80
#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) #define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
#define L2X0_STNDBY_MODE_EN (1 << 0) #define L310_STNDBY_MODE_EN (1 << 0)
/* Registers shifts and masks */ /* Registers shifts and masks */
#define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
@ -88,29 +88,52 @@
#define L310_CACHE_ID_RTL_R3P3 0x09 #define L310_CACHE_ID_RTL_R3P3 0x09
#define L2X0_AUX_CTRL_MASK 0xc0000fff #define L2X0_AUX_CTRL_MASK 0xc0000fff
/* L2C auxiliary control register - bits common to L2C-210/220/310 */
#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
/* L2C-210/220 common bits */
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) #define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 #define L2X0_AUX_CTRL_ASSOC_SHIFT 13
#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 #define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) /* L2C-210 specific bits */
#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 #define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 #define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 #define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 /* L2C-220 specific bits */
#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 #define L220_AUX_CTRL_FWA_SHIFT 23
#define L220_AUX_CTRL_FWA_MASK (3 << 23)
#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
/* L2C-310 specific bits */
#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0 #define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
#define L2X0_LATENCY_CTRL_RD_SHIFT 4 #define L310_LATENCY_CTRL_RD(n) ((n) << 4)
#define L2X0_LATENCY_CTRL_WR_SHIFT 8 #define L310_LATENCY_CTRL_WR(n) ((n) << 8)
#define L2X0_ADDR_FILTER_EN 1 #define L310_ADDR_FILTER_EN 1
#define L2X0_CTRL_EN 1 #define L2X0_CTRL_EN 1

8
arch/arm/mach-cns3xxx/core.c
View file

@ -272,9 +272,9 @@ void __init cns3xxx_l2x0_init(void)
* *
* 1 cycle of latency for setup, read and write accesses * 1 cycle of latency for setup, read and write accesses
*/ */
val = readl(base + L2X0_TAG_LATENCY_CTRL); val = readl(base + L310_TAG_LATENCY_CTRL);
val &= 0xfffff888; val &= 0xfffff888;
writel(val, base + L2X0_TAG_LATENCY_CTRL); writel(val, base + L310_TAG_LATENCY_CTRL);
/* /*
* Data RAM Control register * Data RAM Control register
@ -285,9 +285,9 @@ void __init cns3xxx_l2x0_init(void)
* *
* 1 cycle of latency for setup, read and write accesses * 1 cycle of latency for setup, read and write accesses
*/ */
val = readl(base + L2X0_DATA_LATENCY_CTRL); val = readl(base + L310_DATA_LATENCY_CTRL);
val &= 0xfffff888; val &= 0xfffff888;
writel(val, base + L2X0_DATA_LATENCY_CTRL); writel(val, base + L310_DATA_LATENCY_CTRL);
/* 32 KiB, 8-way, parity disable */ /* 32 KiB, 8-way, parity disable */
l2x0_init(base, 0x00540000, 0xfe000fff); l2x0_init(base, 0x00540000, 0xfe000fff);

8
arch/arm/mach-exynos/sleep.S
View file

@ -65,13 +65,13 @@ ENTRY(exynos_cpu_resume)
ldr r2, [r0, #L2X0_R_AUX_CTRL] ldr r2, [r0, #L2X0_R_AUX_CTRL]
str r2, [r1, #L2X0_AUX_CTRL] str r2, [r1, #L2X0_AUX_CTRL]
ldr r2, [r0, #L2X0_R_TAG_LATENCY] ldr r2, [r0, #L2X0_R_TAG_LATENCY]
str r2, [r1, #L2X0_TAG_LATENCY_CTRL] str r2, [r1, #L310_TAG_LATENCY_CTRL]
ldr r2, [r0, #L2X0_R_DATA_LATENCY] ldr r2, [r0, #L2X0_R_DATA_LATENCY]
str r2, [r1, #L2X0_DATA_LATENCY_CTRL] str r2, [r1, #L310_DATA_LATENCY_CTRL]
ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
str r2, [r1, #L2X0_PREFETCH_CTRL] str r2, [r1, #L310_PREFETCH_CTRL]
ldr r2, [r0, #L2X0_R_PWR_CTRL] ldr r2, [r0, #L2X0_R_PWR_CTRL]
str r2, [r1, #L2X0_POWER_CTRL] str r2, [r1, #L310_POWER_CTRL]
mov r2, #1 mov r2, #1
str r2, [r1, #L2X0_CTRL] str r2, [r1, #L2X0_CTRL]
skip_l2_resume: skip_l2_resume:

8
arch/arm/mach-imx/system.c
View file

@ -124,7 +124,7 @@ void __init imx_init_l2cache(void)
} }
/* Configure the L2 PREFETCH and POWER registers */ /* Configure the L2 PREFETCH and POWER registers */
val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
val |= 0x70800000; val |= 0x70800000;
/* /*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
@ -137,9 +137,9 @@ void __init imx_init_l2cache(void)
*/ */
if (cpu_is_imx6q()) if (cpu_is_imx6q())
val &= ~(1 << 30 | 1 << 23); val &= ~(1 << 30 | 1 << 23);
writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; val = L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN;
writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); writel_relaxed(val, l2x0_base + L310_POWER_CTRL);
iounmap(l2x0_base); iounmap(l2x0_base);
of_node_put(np); of_node_put(np);

2
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View file

@ -194,7 +194,7 @@ static void save_l2x0_context(void)
if (l2x0_base) { if (l2x0_base) {
val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); val = __raw_readl(l2x0_base + L310_PREFETCH_CTRL);
__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
} }
} }

18
arch/arm/mach-omap2/omap4-common.c
View file

@ -197,15 +197,15 @@ static int __init omap_l2_cache_init(void)
return -ENOMEM; return -ENOMEM;
/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
aux_ctrl = (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 |
(0x1 << 25) | L310_AUX_CTRL_CACHE_REPLACE_RR |
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | L310_AUX_CTRL_NS_LOCKDOWN |
(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)) | L310_AUX_CTRL_NS_INT_CTRL |
(0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | L2C_AUX_CTRL_WAY_SIZE(3) |
(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | L2C_AUX_CTRL_SHARED_OVERRIDE |
(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | L310_AUX_CTRL_DATA_PREFETCH |
(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | L310_AUX_CTRL_INSTR_PREFETCH |
(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT); L310_AUX_CTRL_EARLY_BRESP;
omap_smc1(0x109, aux_ctrl); omap_smc1(0x109, aux_ctrl);

5
arch/arm/mach-prima2/l2x0.c
View file

@ -17,13 +17,12 @@ struct l2x0_aux {
}; };
static const struct l2x0_aux prima2_l2x0_aux __initconst = { static const struct l2x0_aux prima2_l2x0_aux __initconst = {
.val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT, .val = L2C_AUX_CTRL_WAY_SIZE(2),
.mask = 0, .mask = 0,
}; };
static const struct l2x0_aux marco_l2x0_aux __initconst = { static const struct l2x0_aux marco_l2x0_aux __initconst = {
.val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | .val = L2C_AUX_CTRL_WAY_SIZE(2) | L310_AUX_CTRL_ASSOCIATIVITY_16,
(1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
.mask = L2X0_AUX_CTRL_MASK, .mask = L2X0_AUX_CTRL_MASK,
}; };

4
arch/arm/mach-realview/realview_pbx.c
View file

@ -370,8 +370,8 @@ static void __init realview_pbx_init(void)
__io_address(REALVIEW_PBX_TILE_L220_BASE); __io_address(REALVIEW_PBX_TILE_L220_BASE);
/* set RAM latencies to 1 cycle for eASIC */ /* set RAM latencies to 1 cycle for eASIC */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL); writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL); writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
/* 16KB way size, 8-way associativity, parity disabled /* 16KB way size, 8-way associativity, parity disabled
* Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */ * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */

6
arch/arm/mach-spear/spear13xx.c
View file

@ -38,14 +38,14 @@ void __init spear13xx_l2x0_init(void)
if (!IS_ENABLED(CONFIG_CACHE_L2X0)) if (!IS_ENABLED(CONFIG_CACHE_L2X0))
return; return;
writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
/* /*
* Program following latencies in order to make * Program following latencies in order to make
* SPEAr1340 work at 600 MHz * SPEAr1340 work at 600 MHz
*/ */
writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
} }

8
arch/arm/mach-sti/board-dt.c
View file

@ -19,10 +19,10 @@ void __init stih41x_l2x0_init(void)
u32 way_size = 0x4; u32 way_size = 0x4;
u32 aux_ctrl; u32 aux_ctrl;
/* may be this can be encoded in macros like BIT*() */ /* may be this can be encoded in macros like BIT*() */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | L310_AUX_CTRL_DATA_PREFETCH |
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | L310_AUX_CTRL_INSTR_PREFETCH |
(way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); L2C_AUX_CTRL_WAY_SIZE(way_size);
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
} }

8
arch/arm/mach-tegra/sleep.h
View file

@ -134,13 +134,13 @@
tst \tmp3, #L2X0_CTRL_EN tst \tmp3, #L2X0_CTRL_EN
bne exit_l2_resume bne exit_l2_resume
ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY] ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL] str \tmp3, [\tmp2, #L310_TAG_LATENCY_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY] ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL] str \tmp3, [\tmp2, #L310_DATA_LATENCY_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL] ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL] str \tmp3, [\tmp2, #L310_PREFETCH_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL] ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
str \tmp3, [\tmp2, #L2X0_POWER_CTRL] str \tmp3, [\tmp2, #L310_POWER_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL] ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
str \tmp3, [\tmp2, #L2X0_AUX_CTRL] str \tmp3, [\tmp2, #L2X0_AUX_CTRL]
mov \tmp3, #L2X0_CTRL_EN mov \tmp3, #L2X0_CTRL_EN

4
arch/arm/mach-ux500/cache-l2x0.c
View file

@ -51,10 +51,10 @@ static int __init ux500_l2x0_init(void)
/* DBx540's L2 has 128KB way size */ /* DBx540's L2 has 128KB way size */
if (cpu_is_ux540_family()) if (cpu_is_ux540_family())
/* 128KB way size */ /* 128KB way size */
aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); aux_val |= L2C_AUX_CTRL_WAY_SIZE(4);
else else
/* 64KB way size */ /* 64KB way size */
aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); aux_val |= L2C_AUX_CTRL_WAY_SIZE(3);
/* 64KB way size, 8 way associativity, force WA */ /* 64KB way size, 8 way associativity, force WA */
if (of_have_populated_dt()) if (of_have_populated_dt())

4
arch/arm/mach-vexpress/ct-ca9x4.c
View file

@ -145,8 +145,8 @@ static void __init ct_ca9x4_init(void)
void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
/* set RAM latencies to 1 cycle for this core tile. */ /* set RAM latencies to 1 cycle for this core tile. */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL); writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL); writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
#endif #endif

57
arch/arm/mm/cache-l2x0.c
View file

@ -576,13 +576,13 @@ static void __init l2c310_save(void __iomem *base)
unsigned revision; unsigned revision;
l2x0_saved_regs.tag_latency = readl_relaxed(base + l2x0_saved_regs.tag_latency = readl_relaxed(base +
L2X0_TAG_LATENCY_CTRL); L310_TAG_LATENCY_CTRL);
l2x0_saved_regs.data_latency = readl_relaxed(base + l2x0_saved_regs.data_latency = readl_relaxed(base +
L2X0_DATA_LATENCY_CTRL); L310_DATA_LATENCY_CTRL);
l2x0_saved_regs.filter_end = readl_relaxed(base + l2x0_saved_regs.filter_end = readl_relaxed(base +
L2X0_ADDR_FILTER_END); L310_ADDR_FILTER_END);
l2x0_saved_regs.filter_start = readl_relaxed(base + l2x0_saved_regs.filter_start = readl_relaxed(base +
L2X0_ADDR_FILTER_START); L310_ADDR_FILTER_START);
revision = readl_relaxed(base + L2X0_CACHE_ID) & revision = readl_relaxed(base + L2X0_CACHE_ID) &
L2X0_CACHE_ID_RTL_MASK; L2X0_CACHE_ID_RTL_MASK;
@ -590,12 +590,12 @@ static void __init l2c310_save(void __iomem *base)
/* From r2p0, there is Prefetch offset/control register */ /* From r2p0, there is Prefetch offset/control register */
if (revision >= L310_CACHE_ID_RTL_R2P0) if (revision >= L310_CACHE_ID_RTL_R2P0)
l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
L2X0_PREFETCH_CTRL); L310_PREFETCH_CTRL);
/* From r3p0, there is Power control register */ /* From r3p0, there is Power control register */
if (revision >= L310_CACHE_ID_RTL_R3P0) if (revision >= L310_CACHE_ID_RTL_R3P0)
l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
L2X0_POWER_CTRL); L310_POWER_CTRL);
} }
static void l2c310_resume(void) static void l2c310_resume(void)
@ -607,23 +607,23 @@ static void l2c310_resume(void)
/* restore pl310 setup */ /* restore pl310 setup */
writel_relaxed(l2x0_saved_regs.tag_latency, writel_relaxed(l2x0_saved_regs.tag_latency,
base + L2X0_TAG_LATENCY_CTRL); base + L310_TAG_LATENCY_CTRL);
writel_relaxed(l2x0_saved_regs.data_latency, writel_relaxed(l2x0_saved_regs.data_latency,
base + L2X0_DATA_LATENCY_CTRL); base + L310_DATA_LATENCY_CTRL);
writel_relaxed(l2x0_saved_regs.filter_end, writel_relaxed(l2x0_saved_regs.filter_end,
base + L2X0_ADDR_FILTER_END); base + L310_ADDR_FILTER_END);
writel_relaxed(l2x0_saved_regs.filter_start, writel_relaxed(l2x0_saved_regs.filter_start,
base + L2X0_ADDR_FILTER_START); base + L310_ADDR_FILTER_START);
revision = readl_relaxed(base + L2X0_CACHE_ID) & revision = readl_relaxed(base + L2X0_CACHE_ID) &
L2X0_CACHE_ID_RTL_MASK; L2X0_CACHE_ID_RTL_MASK;
if (revision >= L310_CACHE_ID_RTL_R2P0) if (revision >= L310_CACHE_ID_RTL_R2P0)
l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
L2X0_PREFETCH_CTRL); L310_PREFETCH_CTRL);
if (revision >= L310_CACHE_ID_RTL_R3P0) if (revision >= L310_CACHE_ID_RTL_R3P0)
l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
L2X0_POWER_CTRL); L310_POWER_CTRL);
l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
} }
@ -658,11 +658,11 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
if (revision >= L310_CACHE_ID_RTL_R3P0 && if (revision >= L310_CACHE_ID_RTL_R3P0 &&
revision < L310_CACHE_ID_RTL_R3P2) { revision < L310_CACHE_ID_RTL_R3P2) {
u32 val = readl_relaxed(base + L2X0_PREFETCH_CTRL); u32 val = readl_relaxed(base + L310_PREFETCH_CTRL);
/* I don't think bit23 is required here... but iMX6 does so */ /* I don't think bit23 is required here... but iMX6 does so */
if (val & (BIT(30) | BIT(23))) { if (val & (BIT(30) | BIT(23))) {
val &= ~(BIT(30) | BIT(23)); val &= ~(BIT(30) | BIT(23));
l2c_write_sec(val, base, L2X0_PREFETCH_CTRL); l2c_write_sec(val, base, L310_PREFETCH_CTRL);
errata[n++] = "752271"; errata[n++] = "752271";
} }
} }
@ -759,7 +759,8 @@ static void __init __l2c_init(const struct l2c_init_data *data,
* *
* L2 cache size = number of ways * way size. * L2 cache size = number of ways * way size.
*/ */
way_size_bits = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
L2C_AUX_CTRL_WAY_SIZE_SHIFT;
l2x0_size = ways * (data->way_size_0 << way_size_bits); l2x0_size = ways * (data->way_size_0 << way_size_bits);
fns = data->outer_cache; fns = data->outer_cache;
@ -902,27 +903,27 @@ static void __init l2c310_of_parse(const struct device_node *np,
of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
if (tag[0] && tag[1] && tag[2]) if (tag[0] && tag[1] && tag[2])
writel_relaxed( writel_relaxed(
((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | L310_LATENCY_CTRL_RD(tag[0] - 1) |
((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | L310_LATENCY_CTRL_WR(tag[1] - 1) |
((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), L310_LATENCY_CTRL_SETUP(tag[2] - 1),
l2x0_base + L2X0_TAG_LATENCY_CTRL); l2x0_base + L310_TAG_LATENCY_CTRL);
of_property_read_u32_array(np, "arm,data-latency", of_property_read_u32_array(np, "arm,data-latency",
data, ARRAY_SIZE(data)); data, ARRAY_SIZE(data));
if (data[0] && data[1] && data[2]) if (data[0] && data[1] && data[2])
writel_relaxed( writel_relaxed(
((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | L310_LATENCY_CTRL_RD(data[0] - 1) |
((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | L310_LATENCY_CTRL_WR(data[1] - 1) |
((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), L310_LATENCY_CTRL_SETUP(data[2] - 1),
l2x0_base + L2X0_DATA_LATENCY_CTRL); l2x0_base + L310_DATA_LATENCY_CTRL);
of_property_read_u32_array(np, "arm,filter-ranges", of_property_read_u32_array(np, "arm,filter-ranges",
filter, ARRAY_SIZE(filter)); filter, ARRAY_SIZE(filter));
if (filter[1]) { if (filter[1]) {
writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
l2x0_base + L2X0_ADDR_FILTER_END); l2x0_base + L310_ADDR_FILTER_END);
writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
l2x0_base + L2X0_ADDR_FILTER_START); l2x0_base + L310_ADDR_FILTER_START);
} }
} }
@ -1298,7 +1299,7 @@ static void __init tauros3_save(void __iomem *base)
l2x0_saved_regs.aux2_ctrl = l2x0_saved_regs.aux2_ctrl =
readl_relaxed(base + TAUROS3_AUX2_CTRL); readl_relaxed(base + TAUROS3_AUX2_CTRL);
l2x0_saved_regs.prefetch_ctrl = l2x0_saved_regs.prefetch_ctrl =
readl_relaxed(base + L2X0_PREFETCH_CTRL); readl_relaxed(base + L310_PREFETCH_CTRL);
} }
static void tauros3_resume(void) static void tauros3_resume(void)
@ -1309,7 +1310,7 @@ static void tauros3_resume(void)
writel_relaxed(l2x0_saved_regs.aux2_ctrl, writel_relaxed(l2x0_saved_regs.aux2_ctrl,
base + TAUROS3_AUX2_CTRL); base + TAUROS3_AUX2_CTRL);
writel_relaxed(l2x0_saved_regs.prefetch_ctrl, writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
base + L2X0_PREFETCH_CTRL); base + L310_PREFETCH_CTRL);
l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
} }