staging: mt7621-spi: add mt7621 support
NeilBrown: The code will fail with a warning if asked to transfer more than 32 bytes at a time. So used max_transfer_size interface to tell users about this. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: NeilBrown <neil@brown.name> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
16e556aa10
commit
1ab7f2a435
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@ -122,4 +122,6 @@ source "drivers/staging/mt7621-pinctrl/Kconfig"
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source "drivers/staging/mt7621-gpio/Kconfig"
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source "drivers/staging/mt7621-spi/Kconfig"
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endif # STAGING
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@ -52,3 +52,4 @@ obj-$(CONFIG_PI433) += pi433/
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obj-$(CONFIG_SOC_MT7621) += mt7621-pci/
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obj-$(CONFIG_SOC_MT7621) += mt7621-pinctrl/
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obj-$(CONFIG_SOC_MT7621) += mt7621-gpio/
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obj-$(CONFIG_SOC_MT7621) += mt7621-spi/
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6
drivers/staging/mt7621-spi/Kconfig
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6
drivers/staging/mt7621-spi/Kconfig
Normal file
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@ -0,0 +1,6 @@
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config SPI_MT7621
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tristate "MediaTek MT7621 SPI Controller"
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depends on RALINK
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help
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This selects a driver for the MediaTek MT7621 SPI Controller.
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1
drivers/staging/mt7621-spi/Makefile
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1
drivers/staging/mt7621-spi/Makefile
Normal file
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@ -0,0 +1 @@
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obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
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5
drivers/staging/mt7621-spi/TODO
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5
drivers/staging/mt7621-spi/TODO
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@ -0,0 +1,5 @@
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- general code review and clean up
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- ensure device-tree requirements are documented
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Cc: NeilBrown <neil@brown.name>
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489
drivers/staging/mt7621-spi/spi-mt7621.c
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489
drivers/staging/mt7621-spi/spi-mt7621.c
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@ -0,0 +1,489 @@
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/*
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* spi-mt7621.c -- MediaTek MT7621 SPI controller driver
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*
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* Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
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*
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* Some parts are based on spi-orion.c:
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* Author: Shadi Ammouri <shadi@marvell.com>
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* Copyright (C) 2007-2008 Marvell Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/swab.h>
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#include <ralink_regs.h>
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#define SPI_BPW_MASK(bits) BIT((bits) - 1)
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#define DRIVER_NAME "spi-mt7621"
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/* in usec */
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#define RALINK_SPI_WAIT_MAX_LOOP 2000
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/* SPISTAT register bit field */
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#define SPISTAT_BUSY BIT(0)
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#define MT7621_SPI_TRANS 0x00
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#define SPITRANS_BUSY BIT(16)
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#define MT7621_SPI_OPCODE 0x04
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#define MT7621_SPI_DATA0 0x08
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#define MT7621_SPI_DATA4 0x18
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#define SPI_CTL_TX_RX_CNT_MASK 0xff
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#define SPI_CTL_START BIT(8)
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#define MT7621_SPI_POLAR 0x38
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#define MT7621_SPI_MASTER 0x28
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#define MT7621_SPI_MOREBUF 0x2c
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#define MT7621_SPI_SPACE 0x3c
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#define MT7621_CPHA BIT(5)
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#define MT7621_CPOL BIT(4)
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#define MT7621_LSB_FIRST BIT(3)
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#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
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struct mt7621_spi;
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struct mt7621_spi {
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struct spi_master *master;
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void __iomem *base;
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unsigned int sys_freq;
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unsigned int speed;
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struct clk *clk;
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spinlock_t lock;
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struct mt7621_spi_ops *ops;
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};
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static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
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{
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return spi_master_get_devdata(spi->master);
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}
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static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
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{
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return ioread32(rs->base + reg);
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}
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static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
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{
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iowrite32(val, rs->base + reg);
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}
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static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
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{
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u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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master |= 7 << 29;
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master |= 1 << 2;
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if (duplex)
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master |= 1 << 10;
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else
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master &= ~(1 << 10);
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mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
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}
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static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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int cs = spi->chip_select;
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u32 polar = 0;
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mt7621_spi_reset(rs, cs);
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if (enable)
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polar = BIT(cs);
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mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
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}
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static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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u32 rate;
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u32 reg;
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dev_dbg(&spi->dev, "speed:%u\n", speed);
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rate = DIV_ROUND_UP(rs->sys_freq, speed);
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dev_dbg(&spi->dev, "rate-1:%u\n", rate);
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if (rate > 4097)
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return -EINVAL;
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if (rate < 2)
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rate = 2;
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reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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reg &= ~(0xfff << 16);
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reg |= (rate - 2) << 16;
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rs->speed = speed;
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reg &= ~MT7621_LSB_FIRST;
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if (spi->mode & SPI_LSB_FIRST)
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reg |= MT7621_LSB_FIRST;
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reg &= ~(MT7621_CPHA | MT7621_CPOL);
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switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
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case SPI_MODE_0:
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break;
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case SPI_MODE_1:
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reg |= MT7621_CPHA;
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break;
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case SPI_MODE_2:
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reg |= MT7621_CPOL;
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break;
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case SPI_MODE_3:
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reg |= MT7621_CPOL | MT7621_CPHA;
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break;
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}
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mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
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return 0;
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}
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static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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int i;
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for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
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u32 status;
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status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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if ((status & SPITRANS_BUSY) == 0) {
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return 0;
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}
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cpu_relax();
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
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struct spi_message *m)
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{
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struct mt7621_spi *rs = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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unsigned int speed = spi->max_speed_hz;
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struct spi_transfer *t = NULL;
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int status = 0;
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int i, len = 0;
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int rx_len = 0;
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u32 data[9] = { 0 };
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u32 val;
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mt7621_spi_wait_till_ready(spi);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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const u8 *buf = t->tx_buf;
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if (t->rx_buf)
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rx_len += t->len;
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if (!buf)
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continue;
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if (t->speed_hz < speed)
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speed = t->speed_hz;
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if (WARN_ON(len + t->len > 36)) {
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status = -EIO;
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goto msg_done;
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}
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for (i = 0; i < t->len; i++, len++)
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data[len / 4] |= buf[i] << (8 * (len & 3));
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}
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if (WARN_ON(rx_len > 32)) {
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status = -EIO;
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goto msg_done;
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}
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if (mt7621_spi_prepare(spi, speed)) {
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status = -EIO;
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goto msg_done;
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}
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data[0] = swab32(data[0]);
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if (len < 4)
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data[0] >>= (4 - len) * 8;
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for (i = 0; i < len; i += 4)
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mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
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val = (min_t(int, len, 4) * 8) << 24;
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if (len > 4)
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val |= (len - 4) * 8;
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val |= (rx_len * 8) << 12;
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mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
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mt7621_spi_set_cs(spi, 1);
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val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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val |= SPI_CTL_START;
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mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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mt7621_spi_wait_till_ready(spi);
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mt7621_spi_set_cs(spi, 0);
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for (i = 0; i < rx_len; i += 4)
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data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
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m->actual_length = len + rx_len;
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len = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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u8 *buf = t->rx_buf;
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if (!buf)
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continue;
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for (i = 0; i < t->len; i++, len++)
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buf[i] = data[len / 4] >> (8 * (len & 3));
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}
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msg_done:
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m->status = status;
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spi_finalize_current_message(master);
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return 0;
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}
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static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
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struct spi_message *m)
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{
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struct mt7621_spi *rs = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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unsigned int speed = spi->max_speed_hz;
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struct spi_transfer *t = NULL;
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int status = 0;
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int i, len = 0;
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int rx_len = 0;
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u32 data[9] = { 0 };
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u32 val = 0;
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mt7621_spi_wait_till_ready(spi);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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const u8 *buf = t->tx_buf;
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if (t->rx_buf)
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rx_len += t->len;
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if (!buf)
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continue;
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if (WARN_ON(len + t->len > 16)) {
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status = -EIO;
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goto msg_done;
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}
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for (i = 0; i < t->len; i++, len++)
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data[len / 4] |= buf[i] << (8 * (len & 3));
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if (speed > t->speed_hz)
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speed = t->speed_hz;
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}
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if (WARN_ON(rx_len > 16)) {
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status = -EIO;
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goto msg_done;
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}
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if (mt7621_spi_prepare(spi, speed)) {
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status = -EIO;
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goto msg_done;
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}
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for (i = 0; i < len; i += 4)
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mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
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val |= len * 8;
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val |= (rx_len * 8) << 12;
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mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
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mt7621_spi_set_cs(spi, 1);
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val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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val |= SPI_CTL_START;
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mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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mt7621_spi_wait_till_ready(spi);
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mt7621_spi_set_cs(spi, 0);
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for (i = 0; i < rx_len; i += 4)
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data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
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m->actual_length = rx_len;
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len = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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u8 *buf = t->rx_buf;
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if (!buf)
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continue;
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for (i = 0; i < t->len; i++, len++)
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buf[i] = data[len / 4] >> (8 * (len & 3));
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}
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msg_done:
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m->status = status;
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spi_finalize_current_message(master);
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return 0;
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}
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static int mt7621_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *m)
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{
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struct spi_device *spi = m->spi;
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int cs = spi->chip_select;
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if (cs)
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return mt7621_spi_transfer_full_duplex(master, m);
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return mt7621_spi_transfer_half_duplex(master, m);
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}
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static int mt7621_spi_setup(struct spi_device *spi)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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if ((spi->max_speed_hz == 0) ||
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(spi->max_speed_hz > (rs->sys_freq / 2)))
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spi->max_speed_hz = (rs->sys_freq / 2);
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if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
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dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
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spi->max_speed_hz);
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return -EINVAL;
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}
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return 0;
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}
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static const struct of_device_id mt7621_spi_match[] = {
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{ .compatible = "ralink,mt7621-spi" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mt7621_spi_match);
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static size_t max_transfer_size(struct spi_device *spi)
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{
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return 32;
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}
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static int mt7621_spi_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct spi_master *master;
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struct mt7621_spi *rs;
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unsigned long flags;
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void __iomem *base;
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struct resource *r;
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int status = 0;
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struct clk *clk;
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struct mt7621_spi_ops *ops;
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match = of_match_device(mt7621_spi_match, &pdev->dev);
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if (!match)
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return -EINVAL;
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ops = (struct mt7621_spi_ops *)match->data;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
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status);
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return PTR_ERR(clk);
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}
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status = clk_prepare_enable(clk);
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if (status)
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return status;
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master = spi_alloc_master(&pdev->dev, sizeof(*rs));
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if (master == NULL) {
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dev_info(&pdev->dev, "master allocation failed\n");
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return -ENOMEM;
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}
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master->mode_bits = RT2880_SPI_MODE_BITS;
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master->setup = mt7621_spi_setup;
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master->transfer_one_message = mt7621_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->dev.of_node = pdev->dev.of_node;
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master->num_chipselect = 2;
|
||||
master->max_transfer_size = max_transfer_size;
|
||||
|
||||
dev_set_drvdata(&pdev->dev, master);
|
||||
|
||||
rs = spi_master_get_devdata(master);
|
||||
rs->base = base;
|
||||
rs->clk = clk;
|
||||
rs->master = master;
|
||||
rs->sys_freq = clk_get_rate(rs->clk);
|
||||
rs->ops = ops;
|
||||
dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
|
||||
spin_lock_irqsave(&rs->lock, flags);
|
||||
|
||||
device_reset(&pdev->dev);
|
||||
|
||||
mt7621_spi_reset(rs, 0);
|
||||
|
||||
return spi_register_master(master);
|
||||
}
|
||||
|
||||
static int mt7621_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct mt7621_spi *rs;
|
||||
|
||||
master = dev_get_drvdata(&pdev->dev);
|
||||
rs = spi_master_get_devdata(master);
|
||||
|
||||
clk_disable(rs->clk);
|
||||
spi_unregister_master(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
|
||||
static struct platform_driver mt7621_spi_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mt7621_spi_match,
|
||||
},
|
||||
.probe = mt7621_spi_probe,
|
||||
.remove = mt7621_spi_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(mt7621_spi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("MT7621 SPI driver");
|
||||
MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
|
||||
MODULE_LICENSE("GPL");
|
Loading…
Reference in a new issue